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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
ecc561f0
Commit
ecc561f0
authored
Jul 04, 2013
by
Theodor-Adrian Stana
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working on hwguide
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hwguide-conv-ttl-blo.bib
doc/hwguide/hwguide-conv-ttl-blo.bib
+5
-0
hwguide-conv-ttl-blo.pdf
doc/hwguide/hwguide-conv-ttl-blo.pdf
+0
-0
hwguide-conv-ttl-blo.tex
doc/hwguide/hwguide-conv-ttl-blo.tex
+64
-36
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doc/hwguide/hwguide-conv-ttl-blo.bib
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ecc561f0
...
...
@@ -41,3 +41,8 @@
title = {{Access to board data using SNMP and I2C}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
@misc{white-rabbit,
title = {{White Rabbit}},
howpublished = {\url{http://www.ohwr.org/projects/white-rabbit}}
}
doc/hwguide/hwguide-conv-ttl-blo.pdf
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ecc561f0
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doc/hwguide/hwguide-conv-ttl-blo.tex
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ecc561f0
...
...
@@ -59,6 +59,7 @@
\section*
{
List of Abbreviations
}
\begin{tabular}
{
l l
}
RTM
&
Rear-Transition Module
\\
SFP
&
Small-Form-factor Pluggable (transceiver)
\\
\end{tabular}
...
...
@@ -72,11 +73,32 @@ SFP & Small-Form-factor Pluggable (transceiver) \\
\section
{
Introduction
}
\label
{
sec:intro
}
\textcolor
{
red
}{
\textbf
{
block diag. from PTS userguide
}}
This document presents the hardware of the TTL to blocking converter system (Figure~
\ref
{
fig:conv-sys-bd
}
).
A full pulse conversion system consists of three distinct boards:
\begin{itemize}
\item
CONV-TTL-BLO -- active front module, containing the circuits necessary
to achieve all functionality of the system
\item
CONV-TTL-RTM -- passive rear-transition module (RTM) motherboard, providing the
connections from the CONV-TTL-BLO VME P2 connector to the rear panel
\item
CONV-TTL-RTM-BLO -- piggyback board on the RTM, providing the LEMO connectors
pulse LEDs, and the screws to fix the rear panel
\end{itemize}
\textcolor
{
red
}{
\textbf
{
board pics
}}
\begin{figure}
[h]
\centerline
{
\includegraphics
[width=\textwidth]
{
../userguide/fig/conv-sys-bd
}}
\caption
{
TTL to blocking pulse conversion system
}
\label
{
fig:conv-sys-bd
}
\end{figure}
\textcolor
{
red
}{
\textbf
{
conv-sys diagram and description
}}
The CONV-TTL-BLO can be used standalone without any RTM, if no blocking pulse replication
is needed. This board contains all active circuitry needed to implement the functionalty of
the system, from blocking pulse detection and generation, to communication over I
$^
2
$
C and
time-tagging via White Rabbit
\cite
{
white-rabbit
}
.
An RTM system usually consists of both motherboard and piggyback and provide the
connections to input blocking pulses to the CONV-TTL-BLO.
\textcolor
{
red
}{
\textbf
{
board pics
}}
%------------------------------------------------------------------------------
% SUBSEC: Additional doc
...
...
@@ -90,10 +112,24 @@ SFP & Small-Form-factor Pluggable (transceiver) \\
\end{itemize}
%==============================================================================
% SEC:
Power supplies
% SEC:
CONV-TTL-BLO
%==============================================================================
\section
{
Power supplies
}
\label
{
sec:power
}
\section
{
Front module
}
\label
{
sec:ctb
}
A block diagram of the CONV-TTL-BLO board is shown in Figure!!!.
\begin{figure}
\centerline
{
\includegraphics
[width=.75\textwidth]
{
fig/
}}
\caption
{
Block diagram of CONV-TTL-BLO board
}
\label
{
fig:
}
\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: Power
%------------------------------------------------------------------------------
\subsection
{
Power supplies
}
\label
{
sec:ctb-power
}
\textcolor
{
red
}{
\textbf
{
FPGA PS from VME
}}
...
...
@@ -105,54 +141,46 @@ SFP & Small-Form-factor Pluggable (transceiver) \\
\textcolor
{
red
}{
\textbf
{
Blocking PS
}}
%
==============================================================================
% SEC: Clocks
%
==============================================================================
\section
{
Clock circuits
}
%
------------------------------------------------------------------------------
% S
UBS
EC: Clocks
%
------------------------------------------------------------------------------
\s
ubs
ection
{
Clock circuits
}
\label
{
sec:clocks
}
\textcolor
{
red
}{
\textbf
{
Describe clock circuits
}}
%
==============================================================================
% SEC: TTL pulse rep
%
==============================================================================
\section
{
TTL pulse repetition
}
%
------------------------------------------------------------------------------
% S
UBS
EC: TTL pulse rep
%
------------------------------------------------------------------------------
\s
ubs
ection
{
TTL pulse repetition
}
\label
{
sec:ttl
}
\textcolor
{
red
}{
\textbf
{
Describe TTL pulse rep
}}
%------------------------------------------------------------------------------
% SUBSEC: Input stage
%------------------------------------------------------------------------------
\subsection
{
Input stage
}
\subsubsection
{
Input stage
}
\textcolor
{
red
}{
\textbf
{
Schmitt trigger isolates FPGA
}}
%------------------------------------------------------------------------------
% SUBSEC: Output stage
%------------------------------------------------------------------------------
\subsection
{
Output stage
}
\subsubsection
{
Output stage
}
\textcolor
{
red
}{
\textbf
{
details about output buffers
}}
%
==============================================================================
% SEC: Blocking pulse rep
%
==============================================================================
\section
{
Blocking pulse repetition
}
%
------------------------------------------------------------------------------
% S
UBS
EC: Blocking pulse rep
%
------------------------------------------------------------------------------
\s
ubs
ection
{
Blocking pulse repetition
}
\label
{
sec:blo
}
%------------------------------------------------------------------------------
% SUBSEC: Input stage
%------------------------------------------------------------------------------
\subsection
{
Input stage
}
\subsubsection
{
Input stage
}
\textcolor
{
red
}{
\textbf
{
Max. inp. PW computation
}}
%------------------------------------------------------------------------------
% SUBSEC: Output stage
%------------------------------------------------------------------------------
\subsection
{
Output stage
}
\subsubsection
{
Output stage
}
\textcolor
{
red
}{
\textbf
{
details about output circuit
}}
...
...
@@ -162,16 +190,16 @@ SFP & Small-Form-factor Pluggable (transceiver) \\
\textcolor
{
red
}{
\textbf
{
danger in case of no firmware
}}
%
==============================================================================
%
------------------------------------------------------------------------------
% SEC: Blocking pulse rep
%
==============================================================================
\section
{
SFP connector
}
%
------------------------------------------------------------------------------
\s
ubs
ection
{
SFP connector
}
\label
{
sec:sfp
}
%
==============================================================================
%
------------------------------------------------------------------------------
% SEC: Thermo, flash
%
==============================================================================
\section
{
Thermometer and flash chip
}
%
------------------------------------------------------------------------------
\s
ubs
ection
{
Thermometer and flash chip
}
\label
{
sec:thermo-flash
}
\textcolor
{
red
}{
\textbf
{
thermo in figure!!
}}
...
...
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