Commit 10c69bc1 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

pulse_gen_gp now v2.0

- freq, pulse, delay controllable via ports
parent 3d77c4bf
--==============================================================================
-- CERN (BE-CO-HT)
-- Test module for old repeater boards
-- General-purpose pulse generator
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-02-28
--
-- version: 1.0
-- version: 2.0
--
-- description:
-- description:
--
-- This module generates pulses with configurable frequency, width and delay.
--
-- In order to generate pulses, the module must be enabled via the en_i port.
-- Once en_i is high, pulses are generated at the frequency specified via
-- freq_i, with the width specified via pwidth_i.
--
-- An optional delay can be added before the start of the pulse, via the delay_i
-- port.
--
-- Note that this delay can be set only before the module is enabled.
--
-- freq_i, pwidth_i and delay_i are given in clk_i cycles.
--
-- dependencies:
--
......@@ -30,6 +43,9 @@
--==============================================================================
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
-- 2013 08-15 Theodor Stana t.stana@cern.ch v2.0, delay, pwidth, freq
-- now controllable via
-- inputs (regs, etc.)
--==============================================================================
-- TODO: -
--==============================================================================
......@@ -40,18 +56,22 @@ use ieee.numeric_std.all;
entity pulse_gen_gp is
generic
(
g_pwidth : natural := 200;
g_freq : natural := 400;
g_delay : natural := 0
);
port
(
clk_i : in std_logic;
rst_n_i : in std_logic;
en_i : in std_logic;
pulse_o : out std_logic
-- Input clock and active-low reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Active high enable signal
en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0);
-- Output pulse signal
pulse_o : out std_logic
);
end entity pulse_gen_gp;
......@@ -74,9 +94,14 @@ architecture behav of pulse_gen_gp is
--============================================================================
-- Signal declarations
--============================================================================
signal freq_cnt : unsigned(f_log2_size(g_freq)-1 downto 0);
signal delay_cnt : unsigned(f_log2_size(g_delay)-1 downto 0);
signal delay_en : std_logic;
signal inp_delay : unsigned(31 downto 0);
signal inp_pwidth : unsigned(31 downto 0);
signal inp_freq : unsigned(31 downto 0);
signal freq_cnt : unsigned(31 downto 0);
signal delay_cnt : unsigned(31 downto 0);
signal delay_en : std_logic;
--==============================================================================
-- architecture begin
......@@ -84,29 +109,34 @@ architecture behav of pulse_gen_gp is
begin
--============================================================================
-- Delay logic
-- Convert std_logic_vector inputs to unsigned
--============================================================================
gen_nodelay: if (g_delay = 0) generate
delay_en <= '0';
end generate gen_nodelay;
inp_delay <= unsigned(delay_i);
inp_pwidth <= unsigned(pwidth_i);
inp_freq <= unsigned(freq_i);
gen_delay: if (g_delay > 0) generate
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
elsif (en_i = '1') and (delay_en = '1') then
--============================================================================
-- Delay logic
--============================================================================
p_delay: process (clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
delay_en <= '1';
delay_cnt <= (others => '0');
elsif (en_i = '1') then
if (inp_delay = (inp_delay'range => '0')) then
delay_en <= '0';
elsif (delay_en = '1') then
delay_cnt <= delay_cnt + 1;
if (delay_cnt = g_delay-1) then
if (delay_cnt = inp_delay-1) then
delay_en <= '0';
delay_cnt <= (others => '0');
end if;
end if;
end if;
end process p_delay;
end generate gen_delay;
end if;
end process p_delay;
--============================================================================
-- Pulse generation logic
......@@ -120,9 +150,9 @@ begin
elsif (en_i = '1') and (delay_en = '0') then
freq_cnt <= freq_cnt + 1;
pulse_o <= '0';
if (freq_cnt < g_pwidth) then
if (freq_cnt < inp_pwidth) then
pulse_o <= '1';
elsif (freq_cnt = g_freq-1) then
elsif (freq_cnt = inp_freq-1) then
freq_cnt <= (others => '0');
end if;
end if;
......
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