Skip to content

C
Conv TTL Blocking - Gateware
Commit ce720fdd authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
Browse files
Options

work on multiboot component

parent efeed6c8
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 1615 additions and 0 deletions
hdl/multiboot/rtl/Manifest.py 0 → 100644
View file @ ce720fdd
files = [
"multiboot_regs.vhd",
"multiboot_fsm.vhd",
"xil_multiboot.vhd"
]
hdl/multiboot/rtl/multiboot_fsm.vhd 0 → 100644
View file @ ce720fdd
--==============================================================================
-- CERN (BE-CO-HT)
-- Xilinx MultiBoot FSM
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-08-19 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiboot_fsm is
port
(
-- Clock and reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control register inputs
rdbootsts_i : in std_logic;
wmb_i : in std_logic;
wgb_i : in std_logic;
iprog_i : in std_logic;
-- Multiboot and golden bitstream start addresses
gbbar_i : in std_logic_vector(31 downto 0);
mbbar_i : in std_logic_vector(31 downto 0);
-- Outputs to status register
bootsts_img_o : out std_logic_vector(15 downto 0);
bootsts_valid_o : out std_logic;
-- Data input and outputs for ICAP component
icap_dat_i : in std_logic_vector(15 downto 0);
icap_dat_o : out std_logic_vector(15 downto 0);
-- Active low chip- and write-enable outputs for ICAP component icap_ce_n_o : out std_logic;
icap_ce_n_o : out std_logic;
icap_wr_n_o : out std_logic
);
end entity multiboot_fsm;
architecture behav of multiboot_fsm is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
(
IDLE,
DUMMY,
SYNC_H,
SYNC_L,
GEN_1,
MBA_L,
GEN_2,
MBA_H,
GEN_3,
GBA_L,
GEN_4,
GBA_H,
CMD,
IPROG,
NOP
);
--============================================================================
-- Constant declarations
--============================================================================
--============================================================================
-- Component declarations
--============================================================================
--============================================================================
-- Signal declarations
--============================================================================
signal state : t_state;
signal icap_din : std_logic_vector(15 downto 0);
signal icap_dout : std_logic_vector(15 downto 0);
signal icap_ce_n : std_logic;
signal icap_wr_n : std_logic;
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- I/O logic
--============================================================================
icap_din <= icap_dat_i;
icap_dat_o <= icap_dout;
icap_ce_n_o <= icap_ce_n;
icap_wr_n_o <= icap_wr_n;
--============================================================================
-- FSM logic
--============================================================================
p_fsm : process(clk_i)
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= IDLE;
icap_dout <= (others => '0');
else
case state is
when IDLE =>
if (iprog_i = '1') then
state <= DUMMY;
icap_ce_n <= '0';
icap_wr_n <= '0';
end if;
--====================================================================
-- IPROG sequence
--====================================================================
when DUMMY =>
icap_dout <= x"ffff";
state <= SYNC_H;
when SYNC_H =>
icap_dout <= x"aa99";
state <= SYNC_L;
when SYNC_L =>
icap_dout <= x"5566";
state <= GEN_1;
when GEN_1 =>
icap_dout <= x"3261";
state <= MBA_L;
when MBA_L =>
icap_dout <= mbbar_i(15 downto 0);
state <= GEN_2;
when GEN_2 =>
icap_dout <= x"3281";
state <= MBA_H;
when MBA_H =>
icap_dout <= mbbar_i(31 downto 16);
state <= GEN_3;
when GEN_3 =>
icap_dout <= x"32a1";
state <= GBA_L;
when GBA_L =>
icap_dout <= gbbar_i(15 downto 0);
state <= GEN_4;
when GEN_4 =>
icap_dout <= x"32c1";
state <= GBA_H;
when GBA_H =>
icap_dout <= gbbar_i(31 downto 16);
state <= CMD;
when CMD =>
icap_dout <= x"30a1";
state <= IPROG;
when IPROG =>
icap_dout <= x"000e";
state <= NOP;
when NOP =>
icap_dout <= x"2000";
state <= IDLE;
end case;
end if;
end if;
end process p_fsm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/multiboot/rtl/multiboot_regs.vhd 0 → 100644
View file @ ce720fdd
--==============================================================================
-- CERN (BE-CO-HT)
-- Wishbone registers for xil_multiboot design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description: Implements the control status and address registers and
-- Wishbone interface for the design.
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-08-19 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity multiboot_regs is
port (
-- Clock and reset inputs
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
-- Wishbone ports
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_wmb_o : out std_logic;
multiboot_cr_wgb_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0)
);
end multiboot_regs;
architecture behav of multiboot_regs is
signal multiboot_cr_rdbootsts_int : std_logic;
signal multiboot_cr_wmb_int : std_logic;
signal multiboot_cr_wgb_int : std_logic;
signal multiboot_cr_iprog_int : std_logic;
signal multiboot_sr_bootsts_img_int : std_logic_vector(15 downto 0);
signal multiboot_sr_valid_int : std_logic;
signal multiboot_gbbar_int, multiboot_mbbar_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(1 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic;
begin
-- Some internal signals assignments.
wrdata_reg <= wb_dat_i;
rwaddr_reg <= wb_adr_i;
multiboot_sr_bootsts_img_int <= multiboot_sr_bootsts_img_i;
multiboot_sr_valid_int <= multiboot_sr_valid_i;
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= (others => '0');
ack_in_progress <= '0';
rddata_reg <= (others => '0');
multiboot_cr_rdbootsts_int <= '0';
multiboot_cr_wmb_int <= '0';
multiboot_cr_wgb_int <= '0';
multiboot_cr_iprog_int <= '0';
multiboot_gbbar_int <= (others => '0');
multiboot_mbbar_int <= (others => '0');
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(0) <= ack_sreg(1);
ack_sreg(1) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg is
when "00" =>
if (wb_we_i = '1') then
multiboot_cr_rdbootsts_int <= wrdata_reg(0);
multiboot_cr_wmb_int <= wrdata_reg(1);
multiboot_cr_wgb_int <= wrdata_reg(2);
multiboot_cr_iprog_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= multiboot_cr_rdbootsts_int;
rddata_reg(1) <= multiboot_cr_wmb_int;
rddata_reg(2) <= multiboot_cr_wgb_int;
rddata_reg(3) <= multiboot_cr_iprog_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
end if;
rddata_reg(15 downto 0) <= multiboot_sr_bootsts_img_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= multiboot_sr_valid_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
multiboot_gbbar_int <= wrdata_reg;
end if;
rddata_reg <= multiboot_gbbar_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "11" =>
if (wb_we_i = '1') then
multiboot_mbbar_int <= wrdata_reg;
end if;
rddata_reg <= multiboot_mbbar_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Drive the stall line
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- Read BOOTSTS register
multiboot_cr_rdbootsts_o <= multiboot_cr_rdbootsts_int;
-- Write MultiBoot Bitstream
multiboot_cr_wmb_o <= multiboot_cr_wmb_int;
-- Write Golden Bitstream
multiboot_cr_wgb_o <= multiboot_cr_wgb_int;
-- IPROG
multiboot_cr_iprog_o <= multiboot_cr_iprog_int;
-- GBBAR
multiboot_gbbar_o <= multiboot_gbbar_int;
-- MBBAR
multiboot_mbbar_o <= multiboot_mbbar_int;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end behav;
hdl/multiboot/rtl/multiboot_regs.wb 0 → 100644
View file @ ce720fdd
peripheral {
name = "MultiBoot registers";
hdl_entity = "multiboot_regs";
prefix = "multiboot";
reg {
name = "Control Register";
description = "Contains bits for controlling the MultiBoot module";
prefix = "cr";
field {
name = "Read BOOTSTS register";
prefix = "rdbootsts";
type = BIT;
};
field {
name = "Write MultiBoot Bitstream";
description = "Write a bitstream to Flash at the MultiBoot bitstream address";
prefix = "wmb";
type = BIT;
};
field {
name = "Write Golden Bitstream";
description = "Write a bitstream to Flash at the golden bitstream address";
prefix = "wgb";
type = BIT;
};
field {
name = "IPROG";
description = "Issue the IPROG command to configuration logic";
prefix = "iprog";
type = BIT;
};
};
reg {
name = "Status Register";
description = "Contains the BOOTSTS register image";
prefix = "sr";
field = {
name = "BOOTSTS image";
prefix = "bootsts_img";
type = SLV;
size = 16;
access_dev = WRITE_ONLY;
access_bus = READ_ONLY;
};
};
};
hdl/multiboot/rtl/xil_multiboot.vhd 0 → 100644
View file @ ce720fdd
--==============================================================================
-- CERN (BE-CO-HT)
-- Xilinx MultiBoot core top-level file
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-08-19 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
use work.wishbone_pkg.all;
entity xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out
);
end entity xil_multiboot;
architecture behav of xil_multiboot is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
--============================================================================
-- Component declarations
--============================================================================
-- Register component
component multiboot_regs is
port (
-- Clock and reset inputs
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
-- Wishbone ports
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_wmb_o : out std_logic;
multiboot_cr_wgb_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0)
);
end component multiboot_regs;
-- FSM component
component multiboot_fsm is
port
(
-- Clock and reset inputs
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Control register inputs
rdbootsts_i : in std_logic;
wmb_i : in std_logic;
wgb_i : in std_logic;
iprog_i : in std_logic;
-- Multiboot and golden bitstream start addresses
gbbar_i : in std_logic_vector(31 downto 0);
mbbar_i : in std_logic_vector(31 downto 0);
-- Outputs to status register
bootsts_img_o : out std_logic_vector(15 downto 0);
bootsts_valid_o : out std_logic;
-- Data input and outputs for ICAP component
icap_dat_i : in std_logic_vector(15 downto 0);
icap_dat_o : out std_logic_vector(15 downto 0);
-- Active low chip- and write-enable outputs for ICAP component
icap_ce_n_o : out std_logic;
icap_wr_n_o : out std_logic
);
end component multiboot_fsm;
--============================================================================
-- Signal declarations
--============================================================================
-- Control and status register signals
signal rdbootsts : std_logic;
signal wmb, wgb : std_logic;
signal iprog : std_logic;
signal bootsts_img : std_logic_vector(15 downto 0);
signal sr_valid : std_logic;
signal gbbar, mbbar : std_logic_vector(31 downto 0);
-- ICAP signals
signal icap_ce_n : std_logic;
signal icap_wr_n : std_logic;
signal icap_busy : std_logic;
signal icap_din : std_logic_vector(15 downto 0);
signal icap_dout : std_logic_vector(15 downto 0);
-- FSM signals
signal fsm_icap_din : std_logic_vector(15 downto 0);
signal fsm_icap_dout : std_logic_vector(15 downto 0);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Register component instantiation
--============================================================================
cmp_regs : multiboot_regs
port map
(
rst_n_i => rst_n_i,
clk_sys_i => clk_i,
wb_adr_i => wbs_i.adr(3 downto 2),
wb_dat_i => wbs_i.dat,
wb_dat_o => wbs_o.dat,
wb_cyc_i => wbs_i.cyc,
wb_sel_i => wbs_i.sel,
wb_stb_i => wbs_i.stb,
wb_we_i => wbs_i.we,
wb_ack_o => wbs_o.ack,
wb_stall_o => wbs_o.stall,
multiboot_cr_rdbootsts_o => rdbootsts,
multiboot_cr_wmb_o => wmb,
multiboot_cr_wgb_o => wgb,
multiboot_cr_iprog_o => iprog,
multiboot_sr_bootsts_img_i => bootsts_img,
multiboot_sr_valid_i => sr_valid,
multiboot_gbbar_o => gbbar,
multiboot_mbbar_o => mbbar
);
--============================================================================
-- FSM component instantiation
--============================================================================
cmp_fsm : multiboot_fsm
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
rdbootsts_i => rdbootsts,
wmb_i => wmb,
wgb_i => wgb,
iprog_i => iprog,
gbbar_i => gbbar,
mbbar_i => mbbar,
bootsts_img_o => bootsts_img,
bootsts_valid_o => sr_valid,
icap_dat_i => fsm_icap_din,
icap_dat_o => fsm_icap_dout,
icap_ce_n_o => icap_ce_n,
icap_wr_n_o => icap_wr_n
);
--============================================================================
-- Xilinx ICAP logic
--============================================================================
-- First, bit-flip the data to/from the FSM
icap_din( 0) <= fsm_icap_dout( 7);
icap_din( 1) <= fsm_icap_dout( 6);
icap_din( 2) <= fsm_icap_dout( 5);
icap_din( 3) <= fsm_icap_dout( 4);
icap_din( 4) <= fsm_icap_dout( 3);
icap_din( 5) <= fsm_icap_dout( 2);
icap_din( 6) <= fsm_icap_dout( 1);
icap_din( 7) <= fsm_icap_dout( 0);
icap_din( 8) <= fsm_icap_dout(15);
icap_din( 9) <= fsm_icap_dout(14);
icap_din(10) <= fsm_icap_dout(13);
icap_din(11) <= fsm_icap_dout(12);
icap_din(12) <= fsm_icap_dout(11);
icap_din(13) <= fsm_icap_dout(10);
icap_din(14) <= fsm_icap_dout( 9);
icap_din(15) <= fsm_icap_dout( 8);
fsm_icap_din( 0) <= icap_dout( 7);
fsm_icap_din( 1) <= icap_dout( 6);
fsm_icap_din( 2) <= icap_dout( 5);
fsm_icap_din( 3) <= icap_dout( 4);
fsm_icap_din( 4) <= icap_dout( 3);
fsm_icap_din( 5) <= icap_dout( 2);
fsm_icap_din( 6) <= icap_dout( 1);
fsm_icap_din( 7) <= icap_dout( 0);
fsm_icap_din( 8) <= icap_dout(15);
fsm_icap_din( 9) <= icap_dout(14);
fsm_icap_din(10) <= icap_dout(13);
fsm_icap_din(11) <= icap_dout(12);
fsm_icap_din(12) <= icap_dout(11);
fsm_icap_din(13) <= icap_dout(10);
fsm_icap_din(14) <= icap_dout( 9);
fsm_icap_din(15) <= icap_dout( 8);
-- and instantiate the ICAP component
cmp_icap : ICAP_SPARTAN6
port map
(
CLK => clk_i,
CE => icap_ce_n,
WRITE => icap_wr_n,
I => icap_din,
O => icap_dout,
BUSY => icap_busy
);
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/multiboot/sim/run.do 0 → 100644
View file @ ce720fdd
vlib work
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/genrams/genram_pkg.vhd"
vcom -explicit -93 "~/Projects/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"
vcom -explicit -93 "../rtl/multiboot_regs.vhd"
vcom -explicit -93 "../rtl/multiboot_fsm.vhd"
vcom -explicit -93 "../rtl/xil_multiboot.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -voptargs="+acc" -debugdb -lib work work.testbench
log -r /*
# add wave *
do wave.do
run 4 us
hdl/multiboot/sim/testbench.vhd 0 → 100644
View file @ ce720fdd
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench for Xilinx MultiBoot design
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-08-19
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-08-19 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
use work.wishbone_pkg.all;
entity testbench is
end entity testbench;
architecture behav of testbench is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant c_clk_per : time := 8 ns;
constant c_rst_width : time := 2 us;
--============================================================================
-- Component declarations
--============================================================================
component xil_multiboot is
port
(
-- Clock and reset input ports
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone ports
wbs_i : in t_wishbone_slave_in;
wbs_o : out t_wishbone_slave_out
);
end component xil_multiboot;
component multiboot_regs is
port (
-- Clock and reset inputs
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
-- Wishbone ports
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Fields of control register
multiboot_cr_rdbootsts_o : out std_logic;
multiboot_cr_wmb_o : out std_logic;
multiboot_cr_wgb_o : out std_logic;
multiboot_cr_iprog_o : out std_logic;
-- Fields of status register
multiboot_sr_bootsts_img_i : in std_logic_vector(15 downto 0);
multiboot_sr_valid_i : in std_logic;
-- Fields of bitstream address registers
multiboot_gbbar_o : out std_logic_vector(31 downto 0);
multiboot_mbbar_o : out std_logic_vector(31 downto 0)
);
end component multiboot_regs;
--============================================================================
-- Signal declarations
--============================================================================
signal rst_n, clk : std_logic := '0';
signal wb_adr : std_logic_vector(31 downto 0);
signal wb_dat_in : std_logic_vector(31 downto 0);
signal wb_dat_out : std_logic_vector(31 downto 0);
signal wb_cyc : std_logic;
signal wb_stb : std_logic;
signal wb_we : std_logic;
signal wb_ack : std_logic;
signal wb_stall : std_logic;
signal wb_sel : std_logic_vector(3 downto 0);
signal wbs_in : t_wishbone_slave_in;
signal wbs_out : t_wishbone_slave_out;
signal transfer : std_logic;
signal write : std_logic;
signal adr : std_logic_vector(31 downto 0);
signal dat : std_logic_vector(31 downto 0);
signal rdbootsts : std_logic;
signal wmb, wgb : std_logic;
signal iprog : std_logic;
signal bootsts_img : std_logic_vector(15 downto 0);
signal valid : std_logic;
signal mbbar, gbbar : std_logic_vector(31 downto 0);
signal str : string(1 to 8);
--==============================================================================
-- architecture begin
--==============================================================================
begin
--============================================================================
-- Instantiate UUT
--============================================================================
UUT: xil_multiboot
port map
(
rst_n_i => rst_n,
clk_i => clk,
wbs_i => wbs_in,
wbs_o => wbs_out
);
-- bind Wishbone ports to signals
wbs_in.dat <= wb_dat_out;
wbs_in.adr <= wb_adr;
wbs_in.cyc <= wb_cyc;
wbs_in.stb <= wb_stb;
wbs_in.we <= wb_we;
wbs_out.ack <= wb_ack;
wbs_out.err <= '0';
wbs_out.stall <= wb_stall;
--============================================================================
-- Clock and reset processes
--============================================================================
p_clk : process is
begin
clk <= not clk;
wait for c_clk_per/2;
end process p_clk;
p_rst : process is
begin
rst_n <= '0';
wait for c_rst_width;
rst_n <= '1';
wait;
end process;
--============================================================================
-- Stimuli process
--============================================================================
p_stim : process is
begin
str <= "init ";
adr <= x"00000000";
dat <= x"00000000";
write <= '0';
transfer <= '0';
-- Write to CR
wait for 3 us;
str <= "wr-cr ";
adr <= x"00000000";
dat <= x"00000008";
write <= '1';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- Read from CR
wait for 30 ns;
str <= "rd-cr ";
adr <= x"00000000";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- Read from SR
wait for 30 ns;
str <= "rd-sr ";
valid <= '1';
bootsts_img <= x"f3f3";
adr <= x"00000004";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- write to GBBAR
wait for 30 ns;
str <= "wr-gbbar";
adr <= x"00000008";
dat <= x"0b012345";
write <= '1';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- read from GBBAR
wait for 30 ns;
str <= "rd-gbbar";
adr <= x"00000008";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- write to MBBAR
wait for 30 ns;
str <= "wr-mbbar";
adr <= x"0000000C";
dat <= x"0b024321";
write <= '1';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- read from MBBAR
wait for 30 ns;
str <= "rd-mbbar";
adr <= x"0000000C";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- Read from SR
wait for 30 ns;
str <= "rd-sr ";
valid <= '1';
bootsts_img <= x"3f3f";
adr <= x"00000004";
write <= '0';
transfer <= '1';
wait for c_clk_per;
transfer <= '0';
-- wait indefinitely
wait;
end process p_stim;
--============================================================================
-- Process running the Wishbone master
--============================================================================
p_wbm : process (clk) is
begin
if rising_edge(clk) then
if (rst_n = '0') then
wb_adr <= (others => '0');
wb_dat_out <= (others => '0');
wb_sel <= (others => '0');
wb_stb <= '0';
wb_cyc <= '0';
wb_we <= '0';
else
if (transfer = '1') then
wb_adr <= adr;
wb_dat_out <= dat;
wb_we <= write;
wb_stb <= '1';
wb_cyc <= '1';
elsif (wb_ack = '1') then
wb_stb <= '0';
wb_cyc <= '0';
end if;
end if;
end if;
end process p_wbm;
end architecture behav;
--==============================================================================
-- architecture end
--==============================================================================
hdl/multiboot/sim/transcript 0 → 100644
View file @ ce720fdd
This diff is collapsed.
hdl/multiboot/sim/wave.do 0 → 100644
View file @ ce720fdd
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/clk
add wave -noupdate -radix hexadecimal /testbench/wb_adr
add wave -noupdate -radix hexadecimal /testbench/wb_dat_in
add wave -noupdate -radix hexadecimal /testbench/wb_dat_out
add wave -noupdate /testbench/wb_cyc
add wave -noupdate /testbench/wb_stb
add wave -noupdate /testbench/wb_we
add wave -noupdate /testbench/wb_ack
add wave -noupdate /testbench/wb_stall
add wave -noupdate /testbench/wb_sel
add wave -noupdate /testbench/transfer
add wave -noupdate /testbench/write
add wave -noupdate -radix hexadecimal /testbench/adr
add wave -noupdate -radix hexadecimal /testbench/dat
add wave -noupdate /testbench/rdbootsts
add wave -noupdate /testbench/wmb
add wave -noupdate /testbench/wgb
add wave -noupdate /testbench/iprog
add wave -noupdate -radix hexadecimal /testbench/bootsts_img
add wave -noupdate -radix hexadecimal /testbench/valid
add wave -noupdate -radix hexadecimal /testbench/mbbar
add wave -noupdate -radix hexadecimal /testbench/gbbar
add wave -noupdate /testbench/str
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {3034 ns} 0}
configure wave -namecolwidth 188
configure wave -valuecolwidth 99
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ns} {3718 ns}
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment