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Conv TTL Blocking - Gateware
Commit 861d6e9b authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Changes to i2c docs

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doc/userguide/userguide-conv-ttl-blo.tex
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......@@ -41,7 +41,7 @@
\hline
19-06-2013 & 1.00 & First version \\
21-06-2013 & 1.01 & Added termination resistors to Fig.~\ref{fig:ttl-chan},~\ref{fig:invttl-chan} \\
04-07-2013 & 1.02 & New title page and page layout \\
22-07-2013 & 1.02 & New title page and page layout \\
\hline
\end{tabular}
}
......@@ -365,7 +365,6 @@ pulses.
\noindent Note 2: $V_{IH}$, $V_{IL}$ correspond to the thresholds of input Schmitt triggers. \\
\noindent Note 3: Max. pulse frequency dictated by blocking output max. frequency. \\
\pagebreak
\begin{table}[h]
\caption{Blocking pulse characteristics}
......@@ -392,7 +391,7 @@ pulses.
\end{table}
\noindent Note 1: Pulse amplitude for which a $t_{p,o}$ pulse is replicated at the output. \\
\noindent Note 2: Voltage amplitude between the differential signal lines \\
\noindent Note 2: Voltage amplitude between the differential signal lines. \\
%--------------------------------------------------------------------------------------
% SUBSEC: TTL vs TTL-BAR
......@@ -495,7 +494,7 @@ on the leading edge of the output signal. Jitter appears in the form of pulses b
either 8~ns before or 8~ns after the ideal edge, based on when the input pulse is sampled.
This is shown in Figure~\ref{fig:tpd-jit}.
When SW1.1 is in the \textbf{OFF} (default) position, the giltch filter is disabled and the
When SW1.1 is in the \textbf{OFF} (default) position, the glitch filter is disabled and the
pulse signal is regenerated at the output without being sampled with an on-board clock. This
yields jitter-free pulses at the output, but a glitch on the input will lead to a pulse being
generated at the output.
......@@ -743,7 +742,7 @@ with glitch filter) of the CH1 and CH4 blocking conversions.
%--------------------------------------------------------------------------------------
\subsection{Repeating TTL pulses in TTL-BAR}
When the board has already been plugged in and the switch has been set in, e.g., the
When the board has already been plugged in and the switch has been set in the
\textbf{OFF} position, only TTL-BAR pulses can be input on a front panel replication channel.
If the user desires to input a TTL pulse and repeat it into TTL-BAR, one of the four
general-purpose inverter channels can be used. Figure~\ref{fig:ex-invert-ttl} shows a
......
hdl/elma_i2c/doc/elma_i2c/elma_i2c.bib
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......@@ -9,3 +9,9 @@
title = {{Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores}},
howpublished = {\url{http://cdn.opencores.org/downloads/wbspec_b4.pdf}}
}
@misc{sysmon,
author = "{ELMA}",
title = {{New SysMon User Manual Rev. 1.11}},
howpublished = {\url{http://www.ohwr.org/documents/226}}
}
hdl/elma_i2c/doc/elma_i2c/elma_i2c.tex
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......@@ -40,7 +40,7 @@
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
26-06-2013 & 1.00 & First version \\
26-06-2013 & 0.01 & First draft \\
\hline
\end{tabular}
}
......@@ -76,9 +76,24 @@
\label{sec:intro}
This document describes the \textit{elma\_i2c} module, an I$^2$C to Wishbone
bridge for the VME64x crates. The module implements an I$^2$C slave and translates
the protocol defined by ELMA in \cite{sysmon-i2c} into Wishbone \cite{wb-spec}
accesses to a Wishbone slave device.
bridge HDL core for VME64x crates from ELMA. These crates offer the possibility of accessing
boards in VME slots via either VME, or I$^2$C. Boards not using the VME lines
on a slot can implement the \textit{elma\_i2c} module on an FPGA; implements an
I$^2$C slave and translates I$^2$C accesses into Wishbone \cite{wb-spec} accesses to a
Wishbone slave device.
A typical system where the \textit{elma\_i2c} module is employed is shown in
Figure~\ref{fig:sys}. ELMA VME crates contain a SysMon (system monitor) board~\cite{sysmon},
that is mainly used for monitoring VME voltages and controlling the fans of the VME crate.
The SysMon can be connected to via either a serial connection or Telnet. Then, sending
specific commands (see Section \ref{sec:testing}) via one of the two are translated by the
SysMon into I$^2$C accesses following the protocol described in Section~\ref{sec:elma-i2c}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/sys}}
\caption{Typical system for the \textit{elma\_i2c} module}
\label{fig:sys}
\end{figure}
%==============================================================================
% SEC: Instantiation
......@@ -88,8 +103,8 @@ accesses to a Wishbone slave device.
The ports of the \textit{elma\_i2c} module are shown in Table~\ref{tbl:ports}.
The I$^2$C signals should be connected to tri-state ports, as shown in
Figure~\ref{fig:i2c-ports}, and Wishbone slaves should be connected to the
Wishbone master interface at the \textit{wbm\_*} ports.
Figure~\ref{fig:i2c-ports}; Wishbone slaves should be connected to the
Wishbone master interface ports, prefixed with \textit{wbm}.
\begin{table}[h]
\caption{Ports of \textit{elma\_i2c} module}
......@@ -168,15 +183,99 @@ Wishbone master interface at the \textit{wbm\_*} ports.
% }
%\end{table}
%==============================================================================
% SEC: Testing
%==============================================================================
\section{Testing the \textit{elma\_i2c} module}
\label{sec:testing}
After proper synthesis and download to the FPGA, a Telnet or serial connection
should be made to the SysMon board. Commands can then be sent to the boards via
the SysMon. The two commands relevant for accessing board registers are \textit{readreg}
and \textit{writereg}, outlined in Table~\ref{tbl:cmds}.
\begin{table}[h]
\caption{The \textit{readreg} and \textit{writereg} commands}
\label{tbl:cmds}
\centerline
{
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Command}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
writereg \textit{slot reg val} & Writes the value \textit{val} to register number
\textit{reg} of board in slot number \textit{slot} \\
readreg \textit{slot reg} & Returns the value of register number \textit{reg} of
board in slot number \textit{slot} \\
\hline
\end{tabular}
}
\end{table}
Register (\textit{reg}) numbers in these commands are decimal numbers starting from 1.
The SysMon translates \textit{reg} numbers into word-aligned addresses, thus in order
to obtain the actual register addres, the following relation should be used:
\begin{center}
$ addr = (reg-1)*4 $
\end{center}
Table~\ref{tbl:reg} shows the \textit{reg} numbers of registers in the address
space 0x00 to 0x20.
\begin{table}[h]
\caption{Translating \textit{reg} numbers to addresses}
\label{tbl:reg}
\centerline
{
\begin{tabular}{c c}
\hline
\textbf{\textit{reg}} & \textbf{Address} \\
\hline
1 & 0x00 \\
2 & 0x04 \\
3 & 0x08 \\
4 & 0x0C \\
5 & 0x10 \\
6 & 0x14 \\
7 & 0x18 \\
8 & 0x1C \\
9 & 0x20 \\
\hline
\end{tabular}
}
\end{table}
The example below shows how to connect to an ELMA crate at IP address 1.2.3.4,
obtaining the value of a register at address 0x10 in a board in VME slot 2,
writing the decimal value 12 to the same register and reading it back to check for
proper modification.
\begin{verbatim}
$ telnet 1.2.3.4
Trying 1.2.3.4...
Connected to 1.2.3.4.
Escape character is '^]'.
login:user
password:**********
%>readreg 2 5
Read Data: 00ABCDEF
%>writereg 2 5 12
Done!
%>readreg 2 5
Read Data: 0000000C
\end{verbatim}
%==============================================================================
% SEC: Protocol
%==============================================================================
\pagebreak
\section{ELMA I$^2$C Protocol}
\label{sec:elma-i2c}
Using the I$^2$C lines on the VME P1 connector, one can access boards placed
in a VME crate. In this purpose, ELMA has defined a higher-level protocol
\cite{sysmon-i2c} that uses I$^2$C as a low-level protocol.
in a VME crate. For this purpose, ELMA has defined a higher-level protocol~\cite{sysmon-i2c}
that uses I$^2$C as a low-level protocol.
Figure~\ref{fig:sysmon-wr} shows a write operation from the SysMon to a VME
board. The process starts with the control byte, containing the board's
......@@ -185,7 +284,7 @@ I$^2$C write. After the slave's ACK, the following two bytes send the
12-bit address in little-endian order (most significant byte first).
After the address has been acknowledged, the following four I$^2$C transfers
are used to transmit the 32-bit data to be written to the board register.
Data transmission occurs with the least significant byte first (big-endian).
Data transmission occurs in big-endian order (least significant byte first).
\begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/sysmon-wr}}
......
hdl/elma_i2c/doc/elma_i2c/fig/sys.svg 0 → 100644
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hdl/elma_i2c/doc/i2c_slave/i2c_slave.tex
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