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C
Conv TTL Blocking - Gateware
Commit efb814d3 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc/hdlguide/fig/pulse-rep.svg 0 → 100644
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
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......@@ -42,7 +42,7 @@
\hline
04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\
05-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
07-08-2013 & 1.02 & Added pulse rejection to \textit{ctb\_pulse\_gen} \\
\hline
\end{tabular}
}
......@@ -460,7 +460,7 @@ the output, logic external to the block caters for the different types of signal
that arrive on CONV-TTL-BLO inputs.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{../userguide/fig/pulse-rep}}
\centerline{\includegraphics[width=\textwidth]{fig/pulse-rep}}
\caption{Board-level view of pulse replication mechanism}
\label{fig:pulse-brd}
\end{figure}
......@@ -541,8 +541,9 @@ The folder structure used within the firmware is presented below.
\renewcommand{\labelitemiv}{$\rightarrow$}
\begin{itemize}
\item ip\_cores/
\item conv-ttl-blo/hdl/
\item ../ip\_cores/
\item conv-ttl-blo-gw/doc/
\item conv-ttl-blo-gw/hdl/
\begin{itemize}
\item bicolor\_led\_ctrl/
\begin{itemize}
......@@ -551,7 +552,6 @@ The folder structure used within the firmware is presented below.
\end{itemize}
\item glitch\_filt/
\begin{itemize}
\item doc/
\item rtl/
\begin{itemize}
\item \textit{glitch\_filt.vhd}
......@@ -567,9 +567,9 @@ The folder structure used within the firmware is presented below.
\end{itemize}
\item top/
\begin{itemize}
\item \textit{conv\_ttl\_blo\_v2.vhd}
\item \textit{conv\_ttl\_blo\_v2.ucf}
\end{itemize}
\item \textit{conv\_ttl\_blo.vhd}
\item \textit{conv\_ttl\_blo.ucf}
\end{itemize}
\end{itemize}
}
\item ctb\_pulse\_gen/
......@@ -588,11 +588,6 @@ The folder structure used within the firmware is presented below.
\end{itemize}
\item elma\_i2c/
\begin{itemize}
\item doc/
\begin{itemize}
\item elma\_i2c/
\item i2c\_slave/
\end{itemize}
\item rtl/
\begin{itemize}
\item \textit{i2c\_slave.vhd}
......@@ -602,13 +597,17 @@ The folder structure used within the firmware is presented below.
\end{itemize}
\end{itemize}
The \textit{ip\_cores/} folder contains repository files that the firmware uses, such
as the Wishbone crossbar (\textit{xwb\_crossbar}). The modules that have been developed as
part of the CONV-TTL-BLO project are present in their own folders as sub-nodes of the
\textit{conv-ttl-blo/hdl/} folder. In general, the module files are present under an
\textit{rtl/} sub-folder; documentation files (if any) for the modules appear under a
\textit{doc/} sub-folder. The I$^2$C bridge module folder also contains the instantiated
\textit{i2c\_slave} module and its documentation.
as the Wishbone crossbar (\textit{xwb\_crossbar}).
Documentation such as this HDL guide and some HDL modules developed as part of the
CONV-TTL-BLO Project can be found in the \textit{conv-ttl-blo/doc/} folder.
Modules that have been developed as part of the CONV-TTL-BLO project are present in
their own folders as sub-nodes of the \textit{conv-ttl-blo/hdl/} folder. In general,
the module files are present under an \textit{rtl/} sub-folder. The I$^2$C bridge
module folder also contains the instantiated \textit{i2c\_slave} module.
The \textit{release/} folder is the main folder in the firmware package, as can be seen from the
fact that it is bolded in the folder structure above. It contains top-level files in the
......
hdl/ctb_pulse_gen/rtl/Manifest.py
View file @ efb814d3
files = "ctb_pulse_gen.vhd"
modules = {
"local" : [
"../../glitch_filt",
"../../../../ip_cores/general-cores"
]
"local" : [ "../../glitch_filt" ]
}
hdl/release/syn/Makefile
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hdl/release/syn/conv_ttl_blo.gise
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......@@ -72,34 +72,34 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1375802859" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
</transform>
<transform xil_pn:end_ts="1375802859" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1700432985017783241" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375802859" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-5050901284947628582" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375802859" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375802859" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-2180482239361632071" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375802859" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="-3972139311098429560" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375802859" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896857" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-6206634123545964380" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375802880" xil_pn:in_ck="1354256890318307606" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1375802859">
<transform xil_pn:end_ts="1375896876" xil_pn:in_ck="4832372736998027881" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="8267614965335338665" xil_pn:start_ts="1375896857">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -117,11 +117,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1375802880" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1375802880">
<transform xil_pn:end_ts="1375896876" xil_pn:in_ck="3498961748663175870" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-3953035127305197084" xil_pn:start_ts="1375896876">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1375802891" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1375802880">
<transform xil_pn:end_ts="1375896886" xil_pn:in_ck="4600148398000832553" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7879307074684351365" xil_pn:start_ts="1375896876">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
......@@ -130,7 +130,7 @@
<outfile xil_pn:name="conv_ttl_blo.ngd"/>
<outfile xil_pn:name="conv_ttl_blo_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1375802945" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1375802891">
<transform xil_pn:end_ts="1375896940" xil_pn:in_ck="4600148398000832554" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="2503688751298223818" xil_pn:start_ts="1375896886">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
......@@ -143,7 +143,7 @@
<outfile xil_pn:name="conv_ttl_blo_summary.xml"/>
<outfile xil_pn:name="conv_ttl_blo_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1375802999" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1375802945">
<transform xil_pn:end_ts="1375896995" xil_pn:in_ck="-9057307156948659133" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1375896940">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
......@@ -157,7 +157,7 @@
<outfile xil_pn:name="conv_ttl_blo_pad.txt"/>
<outfile xil_pn:name="conv_ttl_blo_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1375803035" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1375802999">
<transform xil_pn:end_ts="1375897030" xil_pn:in_ck="-336926714118358808" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1375896995">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
......@@ -169,7 +169,7 @@
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1375802999" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1375802988">
<transform xil_pn:end_ts="1375896995" xil_pn:in_ck="4600148398000832422" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1375896984">
<status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/release/syn/conv_ttl_blo.xise
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hdl/release/top/Manifest.py
View file @ efb814d3
......@@ -11,5 +11,6 @@ modules = {
"../../ctb_pulse_gen",
"../../rtm_detector",
"../../bicolor_led_ctrl",
"../../../../../ip_cores/general-cores"
]
}
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