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C
Conv TTL Blocking - Gateware
Commit 54e10870 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Recalced max blo inp pw and made additions to hwguide

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doc/hwguide/fig/conv-ttl-blo-bd.svg
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......
doc/hwguide/hwguide-conv-ttl-blo.bib
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......@@ -23,8 +23,22 @@
howpublished = {\url{https://edms.cern.ch/file/1278535/1/EDA-02446-V2-1_sch.pdf}}
}
@misc{rtmm-sch,
title = {{RTM Motherboard Schematics}},
howpublished = {\url{https://edms.cern.ch/file/1281435/1/EDA-02452-V2-0_sch.pdf}}
}
@misc{rtmp-sch,
title = {{RTM Piggyback Schematics}},
howpublished = {\url{https://edms.cern.ch/file/1178456/1/EDA-02453-V1-0_sch.pdf}}
}
@misc{blo-ps-datasheet,
author = {{Texas Instruments}},
title = {{TPS40210, TPS40211, 4.5~V to 52~V Input Current Mode Boost Controller}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
}
\ No newline at end of file
}
@misc{spec,
title = {{Simple PCIE FMC Carrier (SPEC)}},
howpublished = {\url{http://www.ohwr.org/projects/spec}}
}
doc/hwguide/hwguide-conv-ttl-blo.tex
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doc/userguide/userguide-conv-ttl-blo.tex
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......@@ -380,7 +380,7 @@ pulses.
$V_{IL}$ & Input pulse low-level amplitude & -5 & & & V \\
$V_{OH}$ & Output pulse high-level amplitude (2)& 23 & 24 & 25 & V \\
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 50 & & 2000& ns \\
$t_{p,i}$& Input pulse width & 50 & & 3900& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Min. period of pulse signal & 4.8 & & & ${\mu}s$ \\
$t_r$ & Rise time & 75 & 140 & 225 & ns \\
......
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