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Conv TTL Blocking - Gateware
Commit 0dcd74a0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc/hdl/hdlguide-conv-ttl-blo.bib
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......@@ -30,7 +30,6 @@
@misc{ctb-ug,
author = "Theodor-Adrian Stana",
title = {{CONV-TTL-BLO User Guide}},
day = 25,
month = 06,
year = 2013,
howpublished = {\url{http://www.ohwr.org/documents/263}}
......
doc/hdl/hdlguide-conv-ttl-blo.tex
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......@@ -59,6 +59,14 @@
\section*{List of Abbreviations}
\begin{tabular}{l l}
DAC & Digital-to-Analog Converter \\
FPGA & Field-Programmable Gate Array \\
FSM & Finite-State Machine \\
IC & Integrated Circuit \\
I$^2$C & Inter-Intergrated Circuit (bus) \\
PLL & Phase-Locked Loop \\
SPI & Serial Peripheral Interface \\
VCXO & Voltage-controlled oscillator \\
\end{tabular}
\pagebreak
......@@ -77,10 +85,198 @@ the CONV-TTL-BLO capabilities:
\begin{itemize}
\item pulse detection (on pulse rising edge)
\item fixed-width pulse generation
\item communication via I$^2$C and the ELMA protocol \cite{sysmon-i2c}
\item status retrieval via I$^2$C and the ELMA protocol
\end{itemize}
\subsection{Additional documentation}
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL firmware. Each of the
blocks in the figure is presented in following sections.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/hdl-bd}}
\caption{Block diagram of FPGA firmware}
\label{fig:hdl-bd}
\end{figure}
%------------------------------------------------------------------------------
% SUBSEC: Additional doc
%------------------------------------------------------------------------------
\subsection*{Additional documentation}
\textcolor{red}{\textbf{!!!}}
\begin{itemize}
\item CONV-TTL-BLO User Guide \cite{ctb-ug}
\end{itemize}
%==============================================================================
% SEC: Clocks
%==============================================================================
\section{FPGA Clocks}
\label{sec:clocks}
There are two clock signals input to the FPGA (Figure~\ref{fig:clocks}).
The first is a 20~MHz signal from a VCXO. The second clock signal with a frequency
of 125~MHz is generated on-board via a Texas Instruments PLL IC from a 25~MHz VCXO.
Two DACs are provided on-board for controlling the two VCXOs. The DACs can be
controlled via SPI, but this feature is not yet implemented.
\begin{figure}
\centerline{\includegraphics[width=\textwidth]{fig/clocks}}
\caption{FPGA clock inputs}
\label{fig:clocks}
\end{figure}
Table~\ref{tbl:clocks} lists the clock domains in the firmware.
\begin{table}[h]
\caption{Clock domains}
\label{tbl:clocks}
\centerline
{
\begin{tabular}{c c l}
\hline
\textbf{Clock domain} & \textbf{Frequency} & \multicolumn{1}{c}{\textbf{Comments}} \\
\hline
\textit{clk125} & 125~MHz & Global clock input to all sequential logic \\
\hline
\end{tabular}
}
\end{table}
%==============================================================================
% SEC: Pulse gen
%==============================================================================
\section{Pulse generators}
\label{sec:pulse-gen}
\begin{table}[h]
\caption{Pulse generator blocks}
\label{tbl:pulse-gen}
\centerline
{
\begin{tabular}{l l l}
\hline
\textbf{Entity} & \textit{ctb\_pulse\_gen} & \\
\textbf{Generics} & \textit{g\_pulse\_width} & Width of the output pulse in \textit{clk\_i} cycles \\
& \textit{g\_glitch\_filt\_len} & Length of glitch filter \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textcolor{red}{\textit{glitch\_filt\_en\_n}} & \textcolor{red}{Active-low glitch filter enable} \\
& \textit{en\_i} & Pulse generator enable \\
& \textit{trig\_i} & Pulse trigger \\
& \textit{pulse\_o} & Pulse output \\
\textbf{Usage} & Output pulse & 1.2~${\mu}s$ pulses \\
& Flash pulse LEDs & 96~$ms$ pulses \\
\hline
\end{tabular}
}
\end{table}
The \textit{ctb\_pulse\_gen} (Table~\ref{tbl:pulse-gen}) blocks are twice used in the
CONV-TTL-BLO firmware. First, they are used for generating the output pulses based on
the trigger input. In this case, they are configured for 1.2~${\mu}s$ pulses
(\textit{g\_pulse\_width = 150}, considering the 8~$ns$ clock input).
Second, they are used for blinking the front and rear-panel pulse LEDs
when a pulse is generated. In this second case, the pulse generator blocks are
configured to generate 96~$ms$ pulses (\textit{g\_pulse\_width} $= 12*10^6$), enough
to be visible to the human eye.
In both cases, the logic associated to the blocks is multiplied by six, since
there are six replication channels.
%------------------------------------------------------------------------------
% SUBSEC: Implem
%------------------------------------------------------------------------------
\subsection{Implementation}
\label{sec:pulse-gen-implem}
Figure~\ref{fig:pulse-gen} shows the implementation of the \textit{ctb\_pulse\_gen}
block. It employs a simple counter finite-state machine (FSM) that is used to generate
a fixed-width pulse at the output.
\begin{figure}[h]
\includegraphics[width=\textwidth]{fig/pulse-gen}
\caption{Pulse generator block}
\label{fig:pulse-gen}
\end{figure}
The block contains a glitch filter (Section~\ref{sec:glitch-filt}) that can be used
to decrease sensitivity to glitches in noisy environments. The glitch filter length
can be enabled via the \textit{glitch\_filt\_en\_n} input (connected to SW1.1 on the
CONV-TTL-BLO). The length of the filter can be set via the \textit{g\_glitch\_filt\_len}
generic.
Enabling the glitch filter will lead to the trigger being sampled using \textit{clk125}
and introduces leading-edge jitter on the \textit{pulse\_o} output. To avoid this
leading-edge pulse jitter, the glitch filter can be disabled.
In whatever the case (glitch filter enabled or not), the FSM reacts to the
rising edge of one of its two start inputs. A rising edge on an input starts
the internal counter, which counts up to a maximum value of \textit{g\_pulse\_width}.
The behavior of the outputs are different, depending on the state of the glitch filter.
With the glitch filter disabled, the input pulse enables the
input flip-flop, which starts pulse generation. The pulse signal is then synchronized
in the \textit{clk125} domain and input to the synchronous counter FSM. The rising
edge on \textit{SGF0} triggers the counter, and when the counter reaches the maximum
value it sets the \textit{OGF0} output for one clock cycle, which will reset the
input flip-flop, thus ending the pulse.
With the glitch filter enabled, the rising edge on \textit{SGF1} sets \textit{OGF1},
and this will be kept high until the counter reaches the maximum value.
%------------------------------------------------------------------------------
% SUBSEC: Board-level
%------------------------------------------------------------------------------
\subsection{Board-level view}
\label{sec:pulse-gen-brdlvl}
The use of the pulse generator module is put into perspective in this section.
Figure~\ref{fig:pulse-brd} shows the pulse replication mechanism on the
CONV-TTL-BLO, where the \textit{PG} block is the \textit{ctb\_pulse\_gen} block.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{../ug/fig/pulse-rep}}
\caption{Board-level view of pulse replication mechanism}
\label{fig:pulse-brd}
\end{figure}
Considering that the counter FSM in the \textit{ctb\_pulse\_gen} reacts to
rising edges on its inputs, it can now be understood why the \textit{PG} block
in Section~4.3 of \cite{ctb-ug} expects TTL type pulses at its inputs.
The \textit{no sig. detect} block at the multiplexer input on the TTL-BAR side
detects the lack of a signal by checking for a continuous high level on the line.
This is important when the TTL selection switch is set to TTL-BAR, since no signal
would mean a DC high-level signal appears at the OR gate input and this signal would
inhibit pulses arriving from the blocking side.
\begin{figure}[h]
\centerline{\includegraphics[scale=1]{fig/no-sig-detect}}
\caption{No signal detect block}
\label{fig:no-sig-detect}
\end{figure}
The implementation of the \textit{no sig. detect} block in Figure~\ref{fig:pulse-brd} is
shown in Figure~\ref{fig:no-sig-detect}. The block is implemented as a counter which
keeps the \textit{en\_o} signal high as long as it does not reach its maximum value.
The counter counts up when the \textit{cnt} input is high. By setting the maximum value
of the counter to 12499, it disables the line to the multiplexer if this stays high
for 100~${\mu}s$, thus allowing for blocking pulses at the input of the OR gate. The line
is re-enabled as soon as it goes back low, i.e., when a wire has been plugged in to the
channel.
%==============================================================================
% SEC: Glitch filt
%==============================================================================
\section{Glitch filter}
\label{sec:glitch-filt}
%==============================================================================
% Bibliography
......@@ -89,4 +285,4 @@ the CONV-TTL-BLO capabilities:
\bibliographystyle{ieeetr}
\bibliography{hdlguide-conv-ttl-blo}
\end{document}
\ No newline at end of file
\end{document}
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