Modified top files to support all modifications in register map plus the new burst controller. Note that the burst controller supported in this commit is the one that averages frequency over 1000 pulses

Added new registers to count TTL pulses and Blocking pulses separately for each channel, instead of counting the OR of the two

The description of the CSR.RST bit has been made clearer to show that it is only
active when CSR.RST_UNLOCK = '1'.

OSWR also now contains 32 bits, to allow for 32 switches in addition to the
existing 8 general-purpose ones.

The 125 MHz domain registers are loaded only once the 20 MHz clock domain
registers are loaded. Like this, we avoid having different values in the
registers in the two clock domains.

This makes the doc and module more generic. The modification will be made in
the code as well.

Also added link to OHWR Wiki page for project examples in the same section.

This is to make sure no readouts of erroneous values from this registers
occur due to the register value not being stable at the time the WB read
cycle is requested.

The pulse synchronizer for the latest timestamp load signal implemented
as part of the previous commit was not working, due to a wrongly-connected
signal. The appropriate signal was connected and the pulse synchronization
mechanism seems to work.

The pulse synchronizer makes sure the load pulse to the 125 MHz clock
domain registers generates a pulse to load the registers in the 20 MHz
clock domain, which are the registers that are read via I2C.

The sys err port also activates on PMISSE errors from any channels,
which was an omission in the previous commits, since I was working mainly
on the RS-485 repeater.

Now, the interface is clearer and easier to use. Just connect led_syserr_o
to the ERR bicolor LED on the board.

The memory map has been updated to include the thermometer SDB
descriptor.

Appendix B was added, containing guidelines on how to implement
a pulse repeater with more than six channels.

- added g_with_pulse_cnt
- added g_with_pulse_timetag
- added SR.PMISSE bit for each of the six channels
- made logic more customizable for g_nr_chans < 6
- doc: added reminder to treat board switches in Overview section

Also, update corresponding conv-regs.wb

In addition, the base address of conv-regs has been changed to three hex digits

- BIDR default reset value
- active values of several SR fields (SWITCHES, RTM, etc.)
- formatting in some registers
- also adapted .wb file to account for this

The main logic changes are that the output enable lines are now set after
the internal reset has been spent. This is to make sure that the lines are
only controlled by the FPGA and no erroneous glitches are generated.

Other changes include the addition of the RTM detection lines to the
interface, which are now reflected in the CONV Status Reg, and connecting
the reset from register line, which was previously unconnected.

Then, component instantiations and the SDB declaration for conv_regs have
been moved to the package file (conv_common_gw_pkg).