Add configurable pulse counter generation and timestamp logic

- added g_with_pulse_cnt - added g_with_pulse_timetag - added SR.PMISSE bit for each of the six channels - made logic more customizable for g_nr_chans < 6 - doc: added reminder to treat board switches in Overview section

Add configurable pulse counter generation and timestamp logic
- added g_with_pulse_cnt - added g_with_pulse_timetag - added SR.PMISSE bit for each of the six channels - made logic more customizable for g_nr_chans < 6 - doc: added reminder to treat board switches in Overview section
02b0e7c2 · Theodor-Adrian Stana · 108561a8 · 02b0e7c2 · 02b0e7c2 · 02b0e7c2
Commit 02b0e7c2 authored Aug 18, 2014 by Theodor-Adrian Stana
5 changed files
--- a/doc/conv-common-gw.tex
+++ b/doc/conv-common-gw.tex
@@ -197,6 +197,8 @@ the conversion between the two interfaces.
  \caption{\label{fig:block-diagram} Block diagram of common gateware}
 \end{figure}

+\textcolor{red}{\textbf{SWITCHES CONVENTION}}
+
 %==============================================================================
 % SEC: Clocking
 %==============================================================================

--- a/modules/conv_regs.vhd
+++ b/modules/conv_regs.vhd
@@ -46,8 +46,8 @@ entity conv_regs is
    reg_sr_i2c_err_i                         : in     std_logic;
    reg_sr_i2c_err_load_o                    : out    std_logic;
 -- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
-    reg_sr_pmisse_o                          : out    std_logic;
-    reg_sr_pmisse_i                          : in     std_logic;
+    reg_sr_pmisse_o                          : out    std_logic_vector(5 downto 0);
+    reg_sr_pmisse_i                          : in     std_logic_vector(5 downto 0);
    reg_sr_pmisse_load_o                     : out    std_logic;
 -- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
    reg_cr_rst_unlock_o                      : out    std_logic;
@@ -270,12 +270,7 @@ begin
            rddata_reg(22) <= reg_sr_i2c_wdto_i;
            rddata_reg(23) <= reg_sr_wrpres_i;
            rddata_reg(24) <= reg_sr_i2c_err_i;
-            rddata_reg(25) <= reg_sr_pmisse_i;
-            rddata_reg(26) <= 'X';
-            rddata_reg(27) <= 'X';
-            rddata_reg(28) <= 'X';
-            rddata_reg(29) <= 'X';
-            rddata_reg(30) <= 'X';
+            rddata_reg(30 downto 25) <= reg_sr_pmisse_i;
            rddata_reg(31) <= 'X';
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
@@ -1024,7 +1019,7 @@ begin
 -- I2C communication error
  reg_sr_i2c_err_o <= wrdata_reg(24);
 -- Pulse missed error
-  reg_sr_pmisse_o <= wrdata_reg(25);
+  reg_sr_pmisse_o <= wrdata_reg(30 downto 25);
 -- Reset unlock bit
  reg_cr_rst_unlock_o <= wrdata_reg(0);
 -- Reset bit

--- a/modules/conv_regs.wb
+++ b/modules/conv_regs.wb
@@ -131,9 +131,13 @@ peripheral {
      name = "Pulse missed error";
      description = "1 -- pulse arrived during pulse rejection phase \
                     0 -- idle \
-                     This bit can be cleared by writing a '1' to it";
+                     Bit 0 -- CH1 \
+                     Bit 1 -- CH2 \
+                     etc. \
+                     Each bit can be cleared by writing a '1' to it";
      prefix = "pmisse";
-      type = BIT;
+      type = SLV;
+      size = 6;
      access_dev = READ_WRITE;
      access_bus = READ_WRITE;
      load = LOAD_EXT;

--- a/top/conv_common_gw.vhd
+++ b/top/conv_common_gw.vhd
--- a/top/conv_common_gw_pkg.vhd
+++ b/top/conv_common_gw_pkg.vhd
@@ -39,6 +39,7 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

 use work.wishbone_pkg.all;
+use work.genram_pkg.all;

 package conv_common_gw_pkg is

@@ -70,6 +71,12 @@ package conv_common_gw_pkg is
      -- Pulse generator glitch filter length in number of clk_20_i cycles
      g_pgen_gf_len         : integer := 4;

+      -- Generate logic with pulse counters
+      g_with_pulse_cnt      : boolean;
+
+      -- Generate logic with pulse counters
+      g_with_pulse_timetag   : boolean;
+
      -- Bicolor LED controller signals
      g_bicolor_led_columns : integer := 6;
      g_bicolor_led_lines   : integer := 2
@@ -116,6 +123,7 @@ package conv_common_gw_pkg is
      led_i2c_err_o           : out std_logic;

      -- VME interface
+      vme_sysreset_n_i        : in  std_logic;
      vme_ga_i                : in  std_logic_vector(4 downto 0);
      vme_gap_i               : in  std_logic;

@@ -266,8 +274,8 @@ package conv_common_gw_pkg is
      reg_sr_i2c_err_i                         : in     std_logic;
      reg_sr_i2c_err_load_o                    : out    std_logic;
  -- Ports for BIT field: 'Pulse missed error' in reg: 'SR'
-      reg_sr_pmisse_o                          : out    std_logic;
-      reg_sr_pmisse_i                          : in     std_logic;
+      reg_sr_pmisse_o                          : out    std_logic_vector(5 downto 0);
+      reg_sr_pmisse_i                          : in     std_logic_vector(5 downto 0);
      reg_sr_pmisse_load_o                     : out    std_logic;
  -- Ports for BIT field: 'Reset unlock bit' in reg: 'CR'
      reg_cr_rst_unlock_o                      : out    std_logic;
@@ -400,5 +408,79 @@ package conv_common_gw_pkg is
        date      => x"20140731",
        name      => "conv_regs          ")));

+  ------------------------------------------------------------------------------
+  -- Pulse time-tagging component
+  ------------------------------------------------------------------------------
+  component conv_pulse_timetag is
+    generic
+    (
+    -- Frequency in Hz of the clk_i signal
+      g_clk_rate : positive := 125000000;
+
+    -- Number of repetition channels
+      g_nr_chan  : positive := 6
+    );
+    port
+    (
+    -- Clock and active-low reset
+      clk_i            : in  std_logic;
+      rst_n_i          : in  std_logic;
+
+    -- Asynchronous pulse input
+      pulse_a_i        : in  std_logic_vector(g_nr_chan downto 1);
+
+    -- Time inputs from White Rabbit
+      wr_tm_cycles_i   : in  std_logic_vector(27 downto 0);
+      wr_tm_tai_i      : in  std_logic_vector(39 downto 0);
+      wr_tm_valid_i    : in  std_logic;
+
+    -- Timing inputs from Wishbone-mapped registers
+      wb_tm_tai_l_i    : in  std_logic_vector(31 downto 0);
+      wb_tm_tai_l_ld_i : in  std_logic;
+      wb_tm_tai_h_i    : in  std_logic_vector( 7 downto 0);
+      wb_tm_tai_h_ld_i : in  std_logic;
+
+    -- Timing outputs
+      tm_cycles_o      : out std_logic_vector(27 downto 0);
+      tm_tai_o         : out std_logic_vector(39 downto 0);
+      tm_wrpres_o      : out std_logic;
+      chan_o           : out std_logic_vector(g_nr_chan downto 1);
+
+    -- Ring buffer I/O
+      buf_wr_req_p_o  : out std_logic
+    );
+  end component conv_pulse_timetag;
+
+  ------------------------------------------------------------------------------
+  -- Ring buffer component
+  -- use: buffer time stamps generated by the conv_pulse_timetag component
+  ------------------------------------------------------------------------------
+  component conv_ring_buf is
+    generic
+    (
+      g_data_width : positive;
+      g_size       : positive
+    );
+    port
+    (
+      -- Clocks and reset
+      clk_rd_i       : in  std_logic;
+      clk_wr_i       : in  std_logic;
+      rst_n_a_i      : in  std_logic;
+
+      -- Buffer inputs
+      buf_dat_i      : in  std_logic_vector(g_data_width-1 downto 0);
+      buf_rd_req_i   : in  std_logic;
+      buf_wr_req_i   : in  std_logic;
+      buf_clr_i      : in  std_logic;
+
+      -- Buffer outputs
+      buf_dat_o      : out std_logic_vector(g_data_width-1 downto 0);
+      buf_count_o    : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
+      buf_full_o     : out std_logic;
+      buf_empty_o    : out std_logic
+    );
+  end component conv_ring_buf;
+
 end package conv_common_gw_pkg;