Commit 9fe7ad9d authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana

Fixed small errors in documentation (memory map)

- BIDR default reset value
- active values of several SR fields (SWITCHES, RTM, etc.)
- formatting in some registers
- also adapted .wb file to account for this
parent b2861817
......@@ -40,3 +40,8 @@
title = {{Platform-independent Core Collection webage on Open Hardware Repository}},
howpublished = {\url{http://www.ohwr.org/projects/general-cores/wiki}}
}
@misc{rtm-det,
title = {{Rear Transition Module detection}},
howpublished = {\url{http://www.ohwr.org/projects/conv-ttl-blo/wiki/RTM_board_detection}}
}
......@@ -11,11 +11,13 @@ Base address: 0x00000000
\hline
\endfirsthead
\hline
\textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\
\hline
\endhead
\hline
\endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x0 & \textit{g\_board\_id} & BIDR & Board ID Register\\
0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
......@@ -49,7 +51,7 @@ Base address: 0x00000000
0x7c & 0x00000000 & CH6LTSCYR & Channel 6 Latest Timestamp Cycles Register\\
0x80 & 0x00000000 & CH6LTSTLR & Channel 6 Latest Timestamp TAI Low Register\\
0x84 & 0x00000000 & CH6LTSTHR & Channel 6 Latest Timestamp TAI High Register\\
0x88 & 0x00000000 & LSR & Line Status Register\\
0x88 & (2) & LSR & Line Status Register\\
0x8c & 0x00000000 & MSWR & Multicast Switch Register\\
\end{longtable}
}
......@@ -57,6 +59,9 @@ Base address: 0x00000000
\noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\noindent Note (2): The reset value of the LSR cannot be specified, since it depends on whether a cable
is plugged into the channel or not.
\vspace{11pt}
\subsubsection{BIDR -- Board ID Register}
......@@ -89,7 +94,7 @@ gateware version, the state of the on-board switches and whether an RTM is plugg
BIDR
} [\emph{read-only}]: ID register bits
\\
Reset value: 0x54424c4f
Reset value: \textit{g\_board\_id}
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
......@@ -134,14 +139,14 @@ Leftmost nibble hex value is major release decimal value \\
SWITCHES
} [\emph{read-only}]: Status of on-board switches
\\
0 -- switch is ON \\ 1 -- switch is OFF
1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines~\cite{rtm-det}
\\
0 -- line active \\ 1 -- line inactive
1 -- line active \\ 0 -- line inactive
\end{small}
\item \begin{small}
{\bf
......@@ -1486,15 +1491,15 @@ WRTAG
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}FS[5:0]}\\
\multicolumn{1}{|c}{-} & - & \multicolumn{6}{|c|}{\cellcolor{gray!25}REARFS[5:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONT\_INVTTL[3:2]}\\
\multicolumn{6}{|c|}{\cellcolor{gray!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONT\_INVTTL[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT\_TTL[5:0]}\\
\multicolumn{2}{|c|}{\cellcolor{gray!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{gray!25}FRONT[5:0]}\\
\hline
\end{tabular}
}
......@@ -1502,37 +1507,39 @@ WRTAG
\begin{itemize}
\item \begin{small}
{\bf
FRONT\_TTL
} [\emph{read-only}]: Front panel TTL input state
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board inputBit 0 -- channel 1Bit 1 -- channel 2etc.
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONT\_INVTTL
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board inputBit 0 -- channel 1Bit 1 -- channel 2etc.
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board inputBit 0 -- channel 1Bit 1 -- channel 2etc.
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FS
REARFS
} [\emph{read-only}]: Input failsafe state
\\
High if line is in failsafe mode (no cable plugged in)Bit 0 -- channel 1Bit 1 -- channel 2etc.
High if line is in failsafe mode (no cable plugged in)\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
\vspace{11pt}
\pagebreak
\subsubsection{MSWR -- Multicast Switch Register}
\vspace{11pt}
......@@ -1563,11 +1570,10 @@ High if line is in failsafe mode (no cable plugged in)Bit 0 -- channel 1Bit 1 --
{\bf
BIT
} [\emph{read-only}]: State of MultiCast switches
\\
1 -- switch is ON \\ 0 -- switch is OFF
\end{small}
\item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined
\end{small}
\end{itemize}
......@@ -45,10 +45,10 @@ peripheral {
name = "BIDR";
description = "Board ID Register";
prefix = "bidr";
reset_value = "0x54424c4f";
reset_value = "g_board_id";
field {
name = "ID register bits";
reset_value = "0x54424c4f";
reset_value = "g_board_id";
type = SLV;
size = 32;
access_dev = WRITE_ONLY;
......@@ -77,8 +77,8 @@ peripheral {
};
field {
name = "Status of on-board switches";
description = "0 -- switch is ON \
1 -- switch is OFF";
description = "1 -- switch is ON \
0 -- switch is OFF";
prefix = "switches";
type = SLV;
size = 8;
......@@ -87,8 +87,8 @@ peripheral {
};
field {
name = "RTM detection lines~\\cite{rtm-det}";
description = "0 -- line active \
1 -- line inactive";
description = "1 -- line active \
0 -- line inactive";
prefix = "rtm";
type = SLV;
size = 6;
......@@ -736,9 +736,12 @@ peripheral {
description = "Line Status Register";
prefix = "lsr";
field {
name = "Front panel TTL input state";
description = "Line state at board input\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
prefix = "front_ttl";
name = "Front panel channel input state";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "front";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
......@@ -746,8 +749,11 @@ peripheral {
};
field {
name = "Front panel INV-TTL input state";
description = "Line state at board input\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
prefix = "front_invttl";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "frontinv";
type = SLV;
size = 4;
access_dev = WRITE_ONLY;
......@@ -755,7 +761,10 @@ peripheral {
};
field {
name = "Rear panel input state";
description = "Line state at board input\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
description = "Line state at board input\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "rear";
type = SLV;
size = 6;
......@@ -764,8 +773,11 @@ peripheral {
};
field {
name = "Input failsafe state";
description = "High if line is in failsafe mode (no cable plugged in)\Bit 0 -- channel 1\Bit 1 -- channel 2\etc.";
prefix = "fs";
description = "High if line is in failsafe mode (no cable plugged in)\
Bit 0 -- channel 1\
Bit 1 -- channel 2\
etc.";
prefix = "rearfs";
type = SLV;
size = 6;
access_dev = WRITE_ONLY;
......@@ -778,7 +790,9 @@ peripheral {
description = "Multicast Switch Register";
prefix = "mswr";
field {
name = "State of MultiCast switches";
name = "State of multicast switches";
description = "1 -- switch is ON \
0 -- switch is OFF";
prefix = "bit";
type = SLV;
size = 4;
......
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