This commit solves some issues which were observed when using the
AXI to Wishbone bridge in Zynq UltraScale+ together with mmap in
Python.

In this situation it happens that two read or write access follow
in a very short time interval. Before this commit, the bridge
incorrectly reported always ready on read and write address channels.
When the two accesses followed in rapid succession, the second
one was lost, causing a timeout in the upstream interconnect.

the wishbone package

In wishbone_pkg.vhd, the new g_sdb_name generic was added to
xwb_crossbar instead of xwb_sdb_crossbar. Fixed

- sdb_rom: add parameter g_sdb_name
- xwb_sdb_crossbar: add parameter g_sdb_name
- wishbone_pkg: f_string_fix_len add parameter justify_right
- wishbone_pkg: f_sdb_auto_device add parameter name
- wishbone_pkg: f_sdb_auto_bridge add parameter name

wishbone/wb_gpio_port: match length of gpio_b to gpio_in when g_num_pins is not an exact multiple of 32. Closes #1532

They finally don't help much and they break simulation as Modelsim complains
about types conversion.

Fix it the same way as f_x_to_zero() is fixed in wbgen.

It fixes some functions not well understood by Vivado synthesis

it was de-asserted at wrong value (too early/late). This was making
to misbehave the modules that depend on this signals.

New function expects textfile with binary representation of each word in a
separate line, e.g.:
10011000000000000000000000000000
11010000000000000000000000000000
11010000001000000000000000000000
01111000000000010000000000000000
00111000001000010000000000000000

This for example reduces WRPC SPEC reference design synthesis time from ~26
minutes to ~11 minutes.

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>

wb_onewire_master: propagated CDR_N/O generics up the hierarchy; added assignments to (new) unspecified WB signals
Signed-off-by: Dimitris Lampridis <Dimitris.Lampridis@cern.ch>