This commit solves some issues which were observed when using the
AXI to Wishbone bridge in Zynq UltraScale+ together with mmap in
Python.

In this situation it happens that two read or write access follow
in a very short time interval. Before this commit, the bridge
incorrectly reported always ready on read and write address channels.
When the two accesses followed in rapid succession, the second
one was lost, causing a timeout in the upstream interconnect.