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Platform-independent core collection
Commit 338eeed9 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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genrams/xilinx: remove optimizations for ram initialization 

They finally don't help much and they break simulation as Modelsim complains
about types conversion.
parent ab1ee585
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Showing with 1 addition and 57 deletions
modules/genrams/xilinx/generic_dpram_dualclock.vhd
View file @ 338eeed9
......@@ -93,24 +93,6 @@ architecture syn of generic_dpram_dualclock is
return tmp;
end if;
-- To speed-up most common cases, use dedicated functions
-- 32-bit width
if (g_data_width = 32) then
mem32 := f_load_mem32_from_file(g_init_file, g_size, g_fail_if_file_not_found);
return t_ram_type(mem32);
end if;
-- 16-bit width
if (g_data_width = 16) then
mem16 := f_load_mem16_from_file(g_init_file, g_size, g_fail_if_file_not_found);
return t_ram_type(mem16);
end if;
-- 8-bit width
if (g_data_width = 8) then
mem8 := f_load_mem8_from_file(g_init_file, g_size, g_fail_if_file_not_found);
return t_ram_type(mem8);
end if;
-- Only for "exotic" sizes do the lengthly (in Vivado 2016.4) copying
arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
pos := 0;
while(pos < g_size)loop
......
modules/genrams/xilinx/generic_dpram_sameclock.vhd
View file @ 338eeed9
......@@ -92,24 +92,6 @@ architecture syn of generic_dpram_sameclock is
return tmp;
end if;
-- To speed-up most common cases, use dedicated functions
-- 32-bit width
if (g_data_width = 32) then
mem32 := f_load_mem32_from_file(g_init_file, g_size, g_fail_if_file_not_found);
return t_ram_type(mem32);
end if;
-- 16-bit width
if (g_data_width = 16) then
mem16 := f_load_mem16_from_file(g_init_file, g_size, g_fail_if_file_not_found);
return t_ram_type(mem16);
end if;
-- 8-bit width
if (g_data_width = 8) then
mem8 := f_load_mem8_from_file(g_init_file, g_size, g_fail_if_file_not_found);
return t_ram_type(mem8);
end if;
-- Only for "exotic" sizes do the lengthly (in Vivado 2016.4) copying
arr := f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
pos := 0;
while(pos < g_size)loop
......@@ -126,27 +108,6 @@ architecture syn of generic_dpram_sameclock is
return tmp;
end f_file_to_ramtype;
--impure function InitRamFromFile(fname : in string) return t_ram_type is
-- FILE RamFile : text;
-- variable fline : line;
-- variable RAM : t_ram_type;
-- variable tmp_bv : bit_vector(g_data_width-1 downto 0);
-- variable status : file_open_status;
--begin
-- if(fname = "" or fname = "none") then
-- RAM := (others=>(others=>'0'));
-- return RAM;
-- end if;
-- file_open(status, RamFile, fname, read_mode);
-- for I in t_ram_type'range loop
-- readline(RamFile, fline);
-- read(fline, tmp_bv);
-- RAM(I) := to_stdlogicvector(tmp_bv);
-- end loop;
-- return RAM;
--end function;
function f_is_synthesis return boolean is
begin
-- synthesis translate_off
......@@ -155,6 +116,7 @@ architecture syn of generic_dpram_sameclock is
return true;
end f_is_synthesis;
shared variable ram : t_ram_type := f_file_to_ramtype;
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
......
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