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Platform-independent core collection
Commit 2f75877d authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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genrams: instantiate splitram in generic_dpram

parent 21e552ef
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Showing with 63 additions and 51 deletions
modules/genrams/genram_pkg.vhd
View file @ 2f75877d
......@@ -111,27 +111,6 @@ package genram_pkg is
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram_split
generic (
g_size : natural;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_fail_if_file_not_found : boolean := true);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector(3 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(31 downto 0);
qa_o : out std_logic_vector(31 downto 0);
bweb_i : in std_logic_vector(3 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(31 downto 0);
qb_o : out std_logic_vector(31 downto 0));
end component;
component generic_dpram_mixed
generic (
g_data_a_width : natural;
......
modules/genrams/xilinx/generic_dpram.vhd
View file @ 2f75877d
......@@ -76,6 +76,33 @@ end generic_dpram;
architecture syn of generic_dpram is
constant c_gen_split :boolean := (g_dual_clock = false and g_data_width=32 and
g_with_byte_enable=true and (g_addr_conflict_resolution="dont_care" or
g_addr_conflict_resolution="read_first"));
constant c_gen_sc :boolean := (not c_gen_split) and (not g_dual_clock);
constant c_gen_dc :boolean := g_dual_clock;
component generic_dpram_split
generic (
g_size : natural;
g_addr_conflict_resolution : string := "dont_care";
g_init_file : string := "none";
g_fail_if_file_not_found : boolean := true);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector(3 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(31 downto 0);
qa_o : out std_logic_vector(31 downto 0);
bweb_i : in std_logic_vector(3 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(31 downto 0);
qb_o : out std_logic_vector(31 downto 0));
end component;
component generic_dpram_sameclock
generic (
g_data_width : natural;
......@@ -125,7 +152,36 @@ architecture syn of generic_dpram is
begin
gen_single_clk : if(g_dual_clock = false) generate
-- generic_dpram_split is like generic_dpram_sameclock, but hardcoded to
-- 32-bit data width and split into 4 BRAMs, each of them 8-bit wide. It's
-- better for Xilinx ISE, because it's unable to infer DPRAM with byte-write
-- enables without using huge number of LUTs.
-- Since it's hardcoded to 32-bits data width, we need to keep
-- generic_dpram_sameclock as well. For reasons why generic_dpram_split is
-- hardcoded to 32-bits please check the Note in generic_dpram_split.vhd.
gen_splitram: if c_gen_split generate
U_RAM_SPLIT: generic_dpram_split
generic map(
g_size => g_size,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map(
rst_n_i => rst_n_i,
clk_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_splitram;
gen_single_clk : if c_gen_sc generate
U_RAM_SC: generic_dpram_sameclock
generic map (
g_data_width => g_data_width,
......@@ -151,7 +207,7 @@ begin
end generate gen_single_clk;
gen_dual_clk : if(g_dual_clock = true) generate
gen_dual_clk : if c_gen_dc generate
U_RAM_DC: generic_dpram_dualclock
generic map (
g_data_width => g_data_width,
......
modules/genrams/xilinx/generic_dpram_split.vhd
View file @ 2f75877d
......@@ -134,6 +134,9 @@ architecture syn of generic_dpram_split is
begin
assert (g_addr_conflict_resolution = "read_first" or g_addr_conflict_resolution = "dont_care")
report "generic_dpram_split: only read_first and dont_care supported for now" severity failure;
-- combine byte-write enable with write signals
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
......
modules/wishbone/wb_dpram/xwb_dpram.vhd
View file @ 2f75877d
......@@ -34,7 +34,6 @@ use work.wishbone_pkg.all;
entity xwb_dpram is
generic(
g_splitram : boolean := false;
g_size : natural := 16384;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
......@@ -109,32 +108,8 @@ begin
master_i => slave2_out,
master_o => slave2_in);
GEN_SPLITRAM: if g_splitram = true generate
U_DPRAM : generic_dpram_split
generic map(
g_size => g_size,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_init_file,
g_fail_if_file_not_found => g_must_have_init_file)
port map(
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
-- Port A
bwea_i => s_bwea,
wea_i => s_wea,
aa_i => slave1_in.adr(f_log2_size(g_size)-1 downto 0),
da_i => slave1_in.dat,
qa_o => slave1_out.dat,
-- Port B
bweb_i => s_bweb,
web_i => s_web,
ab_i => slave2_in.adr(f_log2_size(g_size)-1 downto 0),
db_i => slave2_in.dat,
qb_o => slave2_out.dat
);
end generate;
GEN_INITF: if g_splitram = false and g_init_file /= "" and g_init_file /= "none" generate
GEN_INITF: if g_init_file /= "" and g_init_file /= "none" generate
-- Unfortunately stupid ISE has problem with understanding bytesel
-- description in generic_dpram so it instantiates this using numerous LUTs
-- for connecting BRAMs and supporting bytesel. When initialization with
......@@ -168,7 +143,7 @@ begin
);
end generate;
GEN_NO_INITF: if g_splitram = false and (g_init_file = "" or g_init_file = "none") generate
GEN_NO_INITF: if g_init_file = "" or g_init_file = "none" generate
-- This trick splits ram into four 8-bit blocks of RAM. Now the problem ISE
-- has with understanding correctly bytesel is bypassed and the
-- implementation takes almost none LUTs, just BRAMs.
......
modules/wishbone/wishbone_pkg.vhd
View file @ 2f75877d
......@@ -489,7 +489,6 @@ package wishbone_pkg is
function f_xwb_dpram(g_size : natural) return t_sdb_device;
component xwb_dpram
generic (
g_splitram : boolean := false;
g_size : natural;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
......
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