no technical change, cleanup copyright holders

1e91b239 · Grzegorz Daniluk · ec002a60 · 1e91b239 · 1e91b239 · 1e91b239
Commit 1e91b239 authored Dec 13, 2017 by Grzegorz Daniluk
33 changed files
--- a/modules/common/gc_delay_line.vhd
+++ b/modules/common/gc_delay_line.vhd
+-------------------------------------------------------------------------------
+-- Title      : Parametrized delay block
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_delay_line.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/common/gc_frequency_meter.vhd
+++ b/modules/common/gc_frequency_meter.vhd
+-------------------------------------------------------------------------------
+-- Title      : Frequency meter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_frequency_meter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2015 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;

 use ieee.std_logic_1164.all;

--- a/modules/common/gc_prio_encoder.vhd
+++ b/modules/common/gc_prio_encoder.vhd
+-------------------------------------------------------------------------------
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_prio_encoder.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/common/gc_reset.vhd
+++ b/modules/common/gc_reset.vhd
+-------------------------------------------------------------------------------
+-- Title      : Reset synchronizer and generator
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_reset.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;

--- a/modules/common/gc_rr_arbiter.vhd
+++ b/modules/common/gc_rr_arbiter.vhd
+-------------------------------------------------------------------------------
+-- Title      : Round-robin arbiter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_rr_arbiter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/common/gc_single_reset_gen.vhd
+++ b/modules/common/gc_single_reset_gen.vhd
@@ -34,6 +34,7 @@
 -- Public License along with this source; if not, download it
 -- from http://www.gnu.org/licenses/lgpl-2.1.html
 --
+-------------------------------------------------------------------------------

 library ieee;
 use ieee.STD_LOGIC_1164.all;

--- a/modules/common/gc_sync_register.vhd
+++ b/modules/common/gc_sync_register.vhd
+-------------------------------------------------------------------------------
+-- Title      : Parametrized synchronizer
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : gc_sync_register.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2014-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)

--- a/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
+++ b/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd
@@ -16,7 +16,23 @@
 -- TODO:
 -- - implement write queueing and read prefetching (for speed improvement)
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+++ b/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd
+------------------------------------------------------------------------------
+-- Title      : Atmel EBI asynchronous bus <-> Wishbone bridge
+-- Project    : White Rabbit Switch
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2011-09-23
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use work.wishbone_pkg.all;

--- a/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/axi4_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : axi4_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/wb_axi4lite_bridge.vhd
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+++ b/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
+-------------------------------------------------------------------------------
+-- Title      : AXI4Lite-to-WB bridge wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_axi4lite_bridge.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wishbone/wb_dpram/xwb_dpram.vhd
+++ b/modules/wishbone/wb_dpram/xwb_dpram.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wrc_dpram.vhd
 -- Author     : Grzegorz Daniluk
-- Company    : Elproma, CERN
+-- Company    : CERN
 -- Created    : 2011-02-15
 -- Last update: 2017-02-03
 -- Platform   : FPGA-generics
@@ -14,7 +14,23 @@
 --
 -- Dual port RAM with wishbone interface
 -------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
@@ -11,9 +11,23 @@
 -------------------------------------------------------------------------------
 -- Description: Bidirectional GPIO port of configurable width (1 to 256 bits).
 -------------------------------------------------------------------------------
-- Copyright (c) 2010, 2011 CERN
+-- Copyright (c) 2010 - 2017 CERN
 --
-- 
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+++ b/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
+------------------------------------------------------------------------------
+-- Title      : Wishbone GPIO port wrapper
+-- Project    : General Core Collection (gencores) Library
+------------------------------------------------------------------------------
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN BE-Co-HT
+-- Created    : 2010-05-18
+-- Last update: 2017-10-11
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'87
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 - 2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wishbone/wb_simple_timer/wb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/wb_tics.vhd
@@ -4,7 +4,7 @@
 -------------------------------------------------------------------------------
 -- File       : wb_tics.vhd
 -- Author     : Grzegorz Daniluk
-- Company    : Elproma
+-- Company    : CERN
 -- Created    : 2011-04-03
 -- Last update: 2013-09-13
 -- Platform   : FPGA-generics
@@ -15,7 +15,23 @@
 -- takes 1 usec. It is used by ptp-noposix as a replace of gettimeofday()
 -- function.
 -------------------------------------------------------------------------------
-- Copyright (c) 2011 Grzegorz Daniluk
+-- Copyright (c) 2011-2013 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wb_simple_timer/xwb_tics.vhd
+++ b/modules/wishbone/wb_simple_timer/xwb_tics.vhd
+-------------------------------------------------------------------------------
+-- Title      : WhiteRabbit PTP Core tics wrapper
+-- Project    : WhiteRabbit
+-------------------------------------------------------------------------------
+-- File       : xwb_tics.vhd
+-- Author     : Grzegorz Daniluk
+-- Company    : CERN
+-- Created    : 2011-04-03
+-- Last update: 2013-09-13
+-- Platform   : FPGA-generics
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2013 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 -- todo: configurable interrupt, output compare, PWM?

 library ieee;

--- a/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+++ b/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
+-------------------------------------------------------------------------------
+-- Title      : Wishbone Slave Adapter
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_slave_adapter.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Description:
+--
 -- universal "adapter"
 -- pipelined <> classic
 -- word-aligned/byte-aligned address
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/wishbone/wb_spi/wb_spi.vhd
+++ b/modules/wishbone/wb_spi/wb_spi.vhd
+-------------------------------------------------------------------------------
+-- Title      : Wishbone SPI Master
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wb_spi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)

--- a/modules/wishbone/wb_spi/xwb_spi.vhd
+++ b/modules/wishbone/wb_spi/xwb_spi.vhd
+-------------------------------------------------------------------------------
+-- Title      : Wishbone SPI Master wrapper
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : xwb_spi.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
 --------------------------------------------------------------------------------
 --  Modifications:
 --      2016-08-24: by Jan Pospisil (j.pospisil@cern.ch)

--- a/modules/wishbone/wb_uart/uart_async_rx.vhd
+++ b/modules/wishbone/wb_uart/uart_async_rx.vhd
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - receiver
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_rx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wishbone/wb_uart/uart_async_tx.vhd
+++ b/modules/wishbone/wb_uart/uart_async_tx.vhd
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - tranmitter
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_async_tx.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wishbone/wb_uart/uart_baud_gen.vhd
+++ b/modules/wishbone/wb_uart/uart_baud_gen.vhd
+------------------------------------------------------------------------------
+-- Title      : Simple Wishbone UART - baud generator
+-- Project    : General Cores Collection (gencores) library
+------------------------------------------------------------------------------
+-- File       : uart_baud_gen.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generic
+-- Standard   : VHDL'93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wishbone/wb_uart/wb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/wb_simple_uart.vhd
@@ -17,6 +17,22 @@
 --   vice versa).
 -------------------------------------------------------------------------------
 -- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wb_uart/xwb_simple_uart.vhd
+++ b/modules/wishbone/wb_uart/xwb_simple_uart.vhd
@@ -17,6 +17,22 @@
 --   vice versa).
 -------------------------------------------------------------------------------
 -- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wb_vic/wb_vic.vhd
+++ b/modules/wishbone/wb_vic/wb_vic.vhd
@@ -21,7 +21,23 @@
 -- - interrupt is acknowledged by writing to EIC_EOIR register.
 -- - register layout: see wb_vic.wb for details.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wb_vic/xwb_vic.vhd
+++ b/modules/wishbone/wb_vic/xwb_vic.vhd
@@ -21,7 +21,23 @@
 -- - interrupt is acknowledged by writing to EIC_EOIR register.
 -- - register layout: see wb_vic.wb for details.
 -------------------------------------------------------------------------------
-- Copyright (c) 2010 Tomasz Wlostowski
+-- Copyright (c) 2010 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
 -------------------------------------------------------------------------------
 -- Revisions  :
 -- Date        Version  Author          Description

--- a/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_dpssram.vhd
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_dpssram.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wishbone/wbgen2/wbgen2_eic.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_eic.vhd
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_eic.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

--- a/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_async.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_fifo_sync.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+++ b/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : WBGEN components
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wbgen2_pkg.vhd
+-- Author     : Tomasz Wlostowski
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2012 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;
 use ieee.std_logic_1164.all;


--- a/modules/wishbone/wishbone_pkg.vhd
+++ b/modules/wishbone/wishbone_pkg.vhd
+-------------------------------------------------------------------------------
+-- Title      : Wishbone package
+-- Project    : General Cores
+-------------------------------------------------------------------------------
+-- File       : wishbone_pkg.vhd
+-- Company    : CERN
+-- Platform   : FPGA-generics
+-- Standard   : VHDL '93
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2017 CERN
+--
+-- This source file is free software; you can redistribute it
+-- and/or modify it under the terms of the GNU Lesser General
+-- Public License as published by the Free Software Foundation;
+-- either version 2.1 of the License, or (at your option) any
+-- later version.
+--
+-- This source is distributed in the hope that it will be
+-- useful, but WITHOUT ANY WARRANTY; without even the implied
+-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+-- PURPOSE.  See the GNU Lesser General Public License for more
+-- details.
+--
+-- You should have received a copy of the GNU Lesser General
+-- Public License along with this source; if not, download it
+-- from http://www.gnu.org/licenses/lgpl-2.1.html
+-------------------------------------------------------------------------------
+
 library ieee;

 use ieee.std_logic_1164.all;