Skip to content

P
Platform-independent core collection
Commit 96295346 authored by Maciej Lipinski's avatar Maciej Lipinski Committed by Grzegorz Daniluk
Browse files
Options

inferred_sync_fifo: bugfix of almost_full/empty 

it was de-asserted at wrong value (too early/late). This was making
to misbehave the modules that depend on this signals.
parent 6db1d955
Hide whitespace changes
Inline Side-by-side
Showing with 8 additions and 14 deletions
modules/genrams/common/inferred_sync_fifo.vhd
View file @ 96295346
......@@ -220,13 +220,10 @@ begin -- syn
if rst_n_i = '0' then
almost_full_o <= '0';
else
if(usedw = g_almost_full_threshold-1) then
if(we_int = '1' and rd_int = '0') then
almost_full_o <= '1';
elsif(rd_int = '1' and we_int = '0') then
almost_full_o <= '0';
end if;
if(usedw = g_almost_full_threshold-1) and (we_int = '1' and rd_int = '0') then
almost_full_o <= '1';
elsif (usedw = g_almost_full_threshold) and (rd_int = '1' and we_int = '0') then
almost_full_o <= '0';
end if;
end if;
end if;
......@@ -244,13 +241,10 @@ begin -- syn
if rst_n_i = '0' then
almost_empty_o <= '1';
else
if(usedw = g_almost_empty_threshold+1) then
if(rd_int = '1' and we_int = '0') then
almost_empty_o <= '1';
elsif(we_int = '1' and rd_int = '0') then
almost_empty_o <= '0';
end if;
if(usedw = g_almost_empty_threshold+1) and (rd_int = '1' and we_int = '0') then
almost_empty_o <= '1';
elsif (usedw = g_almost_empty_threshold) and (we_int = '1' and rd_int = '0') then
almost_empty_o <= '0';
end if;
end if;
end if;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment