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Platform-independent core collection
Commit d3575021 authored by Jan Pospisil's avatar Jan Pospisil Committed by Dimitris Lampridis
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wb_onewire_master: propagated CDR_N/O generics up the hierarchy; added… 

wb_onewire_master: propagated CDR_N/O generics up the hierarchy; added assignments to (new) unspecified WB signals
Signed-off-by: 's avatarDimitris Lampridis <Dimitris.Lampridis@cern.ch>
parent 73ae91e6
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Showing with 23 additions and 6 deletions
modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
View file @ d3575021
......@@ -37,7 +37,9 @@ entity wb_onewire_master is
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer := 1;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0"
g_ow_btp_overdrive : string := "1.0";
g_CDR_N : integer := 4; -- normal mode
g_CDR_O : integer := 0 -- overdrive mode
);
port (
......@@ -69,7 +71,9 @@ architecture rtl of wb_onewire_master is
generic(
BTP_N : string;
BTP_O : string;
OWN : integer);
OWN : integer;
CDR_N : integer;
CDR_O : integer);
port(
clk : in std_logic;
......@@ -153,7 +157,9 @@ begin -- rtl
generic map (
BTP_N => g_ow_btp_normal,
BTP_O => g_ow_btp_overdrive,
OWN => g_num_ports)
OWN => g_num_ports,
CDR_N => g_CDR_N,
CDR_O => g_CDR_O)
port map (
clk => clk_sys_i,
rst => rst,
......@@ -166,5 +172,10 @@ begin -- rtl
owr_p => owr_pwren_o,
owr_e => owr_en_o,
owr_i => owr_i);
adp_in.err <= '0';
adp_in.rty <= '0';
adp_in.stall <= '0';
end rtl;
modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
View file @ d3575021
......@@ -9,7 +9,9 @@ entity xwb_onewire_master is
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer := 1;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0"
g_ow_btp_overdrive : string := "1.0";
g_CDR_N : integer := 4; -- normal mode
g_CDR_O : integer := 0 -- overdrive mode
);
port(
......@@ -37,7 +39,9 @@ architecture rtl of xwb_onewire_master is
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string;
g_ow_btp_overdrive : string);
g_ow_btp_overdrive : string;
g_CDR_N : integer;
g_CDR_O : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
......@@ -66,7 +70,9 @@ begin -- rtl
g_address_granularity => g_address_granularity,
g_num_ports => g_num_ports,
g_ow_btp_normal => g_ow_btp_normal,
g_ow_btp_overdrive => g_ow_btp_overdrive)
g_ow_btp_overdrive => g_ow_btp_overdrive,
g_CDR_N => g_CDR_N,
g_CDR_O => g_CDR_O)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
......
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