- 29 Sep, 2019 2 commits
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Dimitris Lampridis authored
[hdl] do not filter out falling edges in direct readout. This can be done if necessary by setting the relevant ACAM registers
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Dimitris Lampridis authored
Previous fix did not correctly account for when the most significant bit of a.frac was '1', as it would incorrectly consider it as a negative number. Also updated the header notes.
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- 28 Sep, 2019 1 commit
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Dimitris Lampridis authored
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- 27 Sep, 2019 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 26 Sep, 2019 5 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 24 May, 2019 3 commits
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Dimitris Lampridis authored
The following changes were done: 1. Point all submodules to new OHWR 2. update ddr3-sp6-core to latest master because the previous commit (8618c1e154c322be34cb069b62d8293527744dda) was not available in OHWR. Please test! 3. remove etherbone-core 4. update general-cores to latest master and use the updated gc_ds182x_readout module
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Dimitris Lampridis authored
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Dimitris Lampridis authored
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- 21 Sep, 2018 7 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 17 Sep, 2018 3 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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- 16 Sep, 2018 5 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
fmc_tdc_core: treat int_flag_i as a synchronous signal, added an IODELAY line programmable from the host to adjust the timing. Possible fix for the 131us bug
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Tomasz Wlostowski authored
hdl: don't use the clks_rsts_manager state machine for driving WR DAC, use standard WR dac interface instead
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Tomasz Wlostowski authored
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- 12 Sep, 2018 2 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing
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- 11 Sep, 2018 9 commits
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
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Tomasz Wlostowski authored
rtl/acam_databus_interface: make design fully synchronous, extend read cycle length to ensure correct Empty Flag timing
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