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FMC TDC 1ns 5cha - Gateware
Commit 8cb00631 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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Merge branch 'tom-sep16' into tom-tmp-sep17

parents f1aadd5f 264a6373
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.gitmodules
View file @ 8cb00631
......@@ -10,6 +10,6 @@
[submodule "hdl/ip_cores/gn4124-core"]
path = hdl/ip_cores/gn4124-core
url = git://ohwr.org/hdl-core-lib/gn4124-core.git
[submodule "hdl/ip_cores/etherbone-core"]
path = hdl/ip_cores/etherbone-core
url = git://ohwr.org/hdl-core-lib/etherbone-core.git
[submodule "hdl/ip_cores/ddr3-sp6-core"]
path = hdl/ip_cores/ddr3-sp6-core
url = git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git
ddr3-sp6-core @ 8618c1e1
Subproject commit 8618c1e154c322be34cb069b62d8293527744dda
general-cores @ 4d36bf85
Subproject commit 0545c25b9b89db17db6f6a2c59752418056715bc
Subproject commit 4d36bf859fa6071acf11d86e1d57ab3a65a5f776
gn4124-core @ 017ef8c1
Subproject commit 5ffe9f5344e22262d1badeef21b8426d20948368
Subproject commit 017ef8c1453664414e871a7992496e15951f32fe
wr-cores @ 5bb966b6
Subproject commit c466a66b4d17173d3ee5e18af26a2d263a760aa0
Subproject commit 5bb966b6868537eb1bf1acf3dd04df95985966bb
hdl/rtl/Manifest.py
View file @ 8cb00631
files = [
"tdc_core_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd"
"tdc_core_pkg.vhd",
"acam_databus_interface.vhd",
"acam_timecontrol_interface.vhd",
"carrier_info.vhd",
"clks_rsts_manager.vhd",
"data_engine.vhd",
"data_formatting.vhd",
"decr_counter.vhd",
"fmc_tdc_core.vhd",
"fmc_tdc_mezzanine.vhd",
"free_counter.vhd",
"incr_counter.vhd",
"leds_manager.vhd",
"local_pps_gen.vhd",
"reg_ctrl.vhd",
"start_retrig_ctrl.vhd",
"tdc_eic.vhd",
"wrabbit_sync.vhd",
"fmc_tdc_direct_readout.vhd",
"fmc_tdc_direct_readout_slave.vhd",
"fmc_tdc_direct_readout_slave_pkg.vhd",
"fmc_tdc_wrapper.vhd",
"timestamp_fifo.vhd",
"timestamp_fifo_wb.vhd",
"timestamp_fifo_wbgen2_pkg.vhd",
"timestamp_convert_filter.vhd",
"tdc_dma_channel.vhd",
"tdc_dma_engine.vhd",
"tdc_buffer_control_regs.vhd",
"tdc_buffer_control_regs_wbgen2_pkg.vhd",
"tdc_ts_addsub.vhd",
"tdc_ts_sub.vhd",
"wbgen2_eic_nomask.vhd",
"dma_eic.vhd",
"tdc_onewire_wb.vhd",
"tdc_onewire_wbgen2_pkg.vhd"
];
hdl/rtl/acam_timecontrol_interface.vhd
View file @ 8cb00631
......@@ -52,11 +52,11 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.gencores_pkg.all;
......@@ -66,74 +66,47 @@ use work.gencores_pkg.all;
entity acam_timecontrol_interface is
port
-- INPUTS
-- INPUTS
-- Signals from the clk_rst_manager unit
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- reset
acam_refclk_r_edge_p_i : in std_logic; -- pulse upon ACAM RefClk rising edge
(clk_i : in std_logic; -- 125 MHz clock
rst_i : in std_logic; -- reset
-- upc_p from the WRabbit or the local generator
utc_p_i : in std_logic;
-- upc_p from the WRabbit or the local generator
utc_p_i : in std_logic;
-- Signals from the data_engine unit
state_active_p_i : in std_logic; -- the core ready to follow the ACAM EF
-- Signals from the data_engine unit
state_active_p_i : in std_logic; -- the core ready to follow the ACAM EF
-- Signals from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- signal from GN4124/VME to start following the ACAM chip
-- for tstamps aquisition
deactivate_acq_p_i : in std_logic; -- acquisition deactivated
-- Signals from the reg_ctrl unit
activate_acq_p_i : in std_logic; -- signal from GN4124/VME to start following the ACAM chip
-- for tstamps aquisition
deactivate_acq_p_i : in std_logic; -- acquisition deactivated
-- Signals from the ACAM chip
err_flag_i : in std_logic; -- ACAM error flag, active HIGH; through ACAM config
-- reg 11 is set to report for any HitFIFOs full flags
int_flag_i : in std_logic; -- ACAM interrupt flag, active HIGH; through ACAM config
-- reg 12 it is set to the MSB of Start#
-- OUTPUTS
-- Signals to the ACAM chip
start_from_fpga_o : out std_logic;
-- OUTPUTS
-- Signals to the ACAM chip
start_from_fpga_o : out std_logic;
stop_dis_o : out std_logic;
-- Signals to the
acam_errflag_r_edge_p_o : out std_logic; -- ACAM ErrFlag rising edge
acam_errflag_f_edge_p_o : out std_logic; -- ACAM ErrFlag falling edge
acam_intflag_f_edge_p_o : out std_logic);-- ACAM IntFlag falling edge
stop_dis_o : out std_logic);
end acam_timecontrol_interface;
--=================================================================================================
-- architecture declaration
end entity;
--=================================================================================================
architecture rtl of acam_timecontrol_interface is
signal acam_intflag_f_edge_p : std_logic;
signal start_pulse, wait_for_utc, rst_n, wait_for_state_active : std_logic;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
rst_n <= not(rst_i);
---------------------------------------------------------------------------------------------------
-- IntFlag and ERRflag Input Synchronizers --
---------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
sync_err_flag : gc_sync_ffs
port map (
clk_i => clk_i,
rst_n_i => '1',
data_i => err_flag_i,
ppulse_o => acam_errflag_r_edge_p_o,
npulse_o => acam_errflag_f_edge_p_o);
sync_int_flag : gc_sync_ffs
port map (
clk_i => clk_i,
rst_n_i => '1',
data_i => int_flag_i,
npulse_o => acam_intflag_f_edge_p_o);
rst_n <= not(rst_i);
---------------------------------------------------------------------------------------------------
-- start_from_fpga_o generation --
......@@ -142,18 +115,18 @@ begin
-- after the state_active_p_i (coming from the data_engine unit).
-- The pulse is synchronous to the utc_p_i
start_pulse_from_fpga: process (clk_i)
start_pulse_from_fpga : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' or deactivate_acq_p_i = '1' then
wait_for_utc <= '0';
start_pulse <= '0';
wait_for_state_active <= '0';
stop_dis_o <= '1';
if rst_i = '1' or deactivate_acq_p_i = '1' then
wait_for_utc <= '0';
start_pulse <= '0';
wait_for_state_active <= '0';
stop_dis_o <= '1';
else
if activate_acq_p_i = '1' then
wait_for_utc <= '1';
start_pulse <= '0';
wait_for_utc <= '1';
start_pulse <= '0';
elsif utc_p_i = '1' and wait_for_utc = '1' then
wait_for_utc <= '0';
start_pulse <= '1';
......@@ -163,7 +136,7 @@ begin
stop_dis_o <= '0';
wait_for_state_active <= '0';
else
start_pulse <= '0';
start_pulse <= '0';
end if;
end if;
end if;
......@@ -171,8 +144,8 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
extend_pulse : gc_extend_pulse
generic map (g_width => 4)
port map
generic map (g_width => 4)
port map
(clk_i => clk_i,
rst_n_i => rst_n,
pulse_i => start_pulse,
......
hdl/rtl/build_wb.sh 0 → 100755
View file @ 8cb00631
#!/bin/bash
wbgen2 -V timestamp_fifo_wb.vhd -H record_full -p timestamp_fifo_wbgen2_pkg.vhd -K timestamp_fifo_regs.vh -s defines -C timestamp_fifo_regs.h -D wbgen/timestamp_fifo_wb.html wbgen/timestamp_fifo_wb.wb
wbgen2 -V tdc_onewire_wb.vhd -H record_full -p tdc_onewire_wbgen2_pkg.vhd -K timestamp_onewire_regs.vh -s defines -C tdc_onewire_regs.h wbgen/tdc_onewire_wb.wb
#wbgen2 -V tdc_buffer_control_regs.vhd -H record_full -p tdc_buffer_control_regs_wbgen2_pkg.vhd -K tdc_buffer_control_regs.vh -s defines -C tdc_buffer_control_regs.h wbgen/tdc_buffer_control_regs.wb
#don't do this, latest wbgen is buggy
#wbgen2 -V tdc_eic.vhd -s defines -C tdc_eic.h -D wbgen/tdc_eic.html wbgen/tdc_eic.wb
hdl/rtl/clks_rsts_manager.vhd
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hdl/rtl/data_formatting.vhd
View file @ 8cb00631
......@@ -62,7 +62,7 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
......@@ -96,13 +96,16 @@ entity data_formatting is
retrig_nb_offset_i : in std_logic_vector(31 downto 0);
current_retrig_nb_i : in std_logic_vector(31 downto 0);
gen_fake_ts_enable_i : in std_logic;
gen_fake_ts_period_i : in std_logic_vector(27 downto 0);
gen_fake_ts_channel_i : in std_logic_vector(2 downto 0);
-- Signal from the WRabbit core or the one_hz_generator unit
utc_p_i : in std_logic;
-- OUTPUTS
timestamp_o : out std_logic_vector(127 downto 0);
timestamp_o : out t_acam_timestamp;
timestamp_valid_o : out std_logic
);
......@@ -138,27 +141,36 @@ architecture rtl of data_formatting is
signal un_current_retrig_from_roll_over : unsigned(31 downto 0);
signal un_acam_fine_time : unsigned(31 downto 0);
signal previous_utc : std_logic_vector(31 downto 0);
signal timestamp_valid_int : std_logic;
signal timestamp_valid_int : std_logic;
signal fake_cnt_coarse : unsigned(27 downto 0);
signal fake_cnt_period : unsigned(27 downto 0);
signal fake_cnt_tai : unsigned(31 downto 0);
signal fake_ts_valid : std_logic;
signal timestamp_valid_int_d : std_logic;
signal raw_ts, raw_ts_d : t_raw_acam_timestamp;
--=================================================================================================
-- architecture begin
--=================================================================================================
begin
p_gen_timestamp_valid : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i = '1' then
timestamp_valid_int <= '0';
else
timestamp_valid_int <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
timestamp_valid_int <= acam_tstamp1_ok_p_i or acam_tstamp2_ok_p_i;
timestamp_valid_int_d <= timestamp_valid_int;
end if;
end if;
end process;
---------------------------------------------------------------------------------------------------
-- Final Timestamp Formatting --
-- Final Timestamp Formatting --
---------------------------------------------------------------------------------------------------
-- tstamp_formatting: slicing of the 32-bits word acam_tstamp1_i and acam_tstamp2_i as received
-- from the data_engine unit, to construct the final timestamps to be stored in the circular_buffer
......@@ -212,6 +224,26 @@ begin
end if;
end process;
p_tstamp_raw_latch : process(clk_i)
begin
if rising_edge(clk_i) then
if timestamp_valid_int = '1' then
raw_ts.seconds <= utc_i;
raw_ts.acam_bins <= acam_fine_timestamp;
raw_ts.acam_start_nb <= std_logic_vector(acam_start_nb);
raw_ts.slope <= acam_slope;
raw_ts.channel <= acam_channel;
raw_ts.roll_over_incr_recent <= roll_over_incr_recent_i;
raw_ts.clk_i_cycles_offset <= clk_i_cycles_offset_i(7 downto 0);
raw_ts.roll_over_nb <= roll_over_nb_i(15 downto 0);
raw_ts.retrig_nb_offset <= retrig_nb_offset_i(8 downto 0);
raw_ts.current_retrig_nb <= current_retrig_nb_i(8 downto 0);
end if;
raw_ts_d <= raw_ts;
end if;
end process;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
reg_info_of_previous_sec : process (clk_i)
begin
......@@ -233,11 +265,12 @@ begin
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- all the values needed for the calculations have to be converted to unsigned
un_acam_fine_time <= unsigned(fine_time);
acam_start_nb_32 <= x"000000" & acam_start_nb;
un_acam_start_nb <= unsigned(acam_start_nb_32);
un_current_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
un_current_roll_over_nb <= unsigned(roll_over_nb_i);
un_acam_fine_time <= unsigned(fine_time);
acam_start_nb_32 <= x"000000" & acam_start_nb;
un_acam_start_nb <= unsigned(acam_start_nb_32);
un_current_retrig_nb_offset <= unsigned(retrig_nb_offset_i);
un_current_roll_over_nb <= unsigned(roll_over_nb_i);
un_current_retrig_from_roll_over <= shift_left(un_current_roll_over_nb-1, 8) when roll_over_incr_recent_i = '1' and un_acam_start_nb > 192 and un_current_roll_over_nb > 0
else shift_left(un_current_roll_over_nb, 8);
......@@ -335,20 +368,63 @@ begin
metadata(2 downto 0) <= acam_channel;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
full_timestamp(31 downto 0) <= fine_time;
full_timestamp(63 downto 32) <= coarse_time;
full_timestamp(95 downto 64) <= utc;
full_timestamp(127 downto 96) <= metadata;
process(clk_i)
begin
if rising_edge(clk_i) then
if gen_fake_ts_enable_i = '0' then
fake_cnt_coarse <= (others => '0');
fake_cnt_tai <= (others => '0');
fake_cnt_period <= (others => '0');
else
if unsigned(gen_fake_ts_period_i) = fake_cnt_period then
fake_cnt_period <= (others => '0');
fake_ts_valid <= '1';
else
fake_cnt_period <= fake_cnt_period + 1;
fake_ts_valid <= '0';
end if;
if fake_cnt_coarse = 124999999 then
fake_cnt_coarse <= (others => '0');
fake_cnt_tai <= fake_cnt_tai + 1;
else
fake_cnt_coarse <= fake_cnt_coarse + 1;
end if;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
timestamp_o <= full_timestamp;
timestamp_valid_o <= timestamp_valid_int;
if rst_i = '1' then
else
if(gen_fake_ts_enable_i = '1' and fake_ts_valid = '1')then
timestamp_o.slope <= '1';
timestamp_o.channel <= gen_fake_ts_channel_i;
timestamp_o.n_bins <= (others => '0');
timestamp_o.coarse <= std_logic_vector(resize(fake_cnt_coarse, 32));
timestamp_o.tai <= std_logic_vector(fake_cnt_tai);
timestamp_valid_o <= '1';
elsif(timestamp_valid_int_d = '1') then
timestamp_o.raw <= raw_ts_d;
timestamp_o.slope <= acam_slope;
timestamp_o.channel <= acam_channel;
timestamp_o.n_bins <= fine_time(16 downto 0);
timestamp_o.coarse <= coarse_time;
timestamp_o.tai <= utc(31 downto 0);
timestamp_o.meta <= x"000" & std_logic_vector(acam_start_nb(6 downto 0)) & fine_time(12 downto 0);
timestamp_valid_o <= '1';
else
timestamp_valid_o <= '0';
end if;
end if;
end if;
end process;
end rtl;
----------------------------------------------------------------------------------------------------
-- architecture ends
......
hdl/rtl/dma_eic.vhd 0 → 100644
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hdl/rtl/fmc_tdc_core.vhd
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hdl/rtl/fmc_tdc_mezzanine.vhd
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hdl/rtl/fmc_tdc_wrapper.vhd
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hdl/rtl/leds_manager.vhd
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hdl/rtl/reg_ctrl.vhd
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hdl/rtl/start_retrig_ctrl.vhd
View file @ 8cb00631
......@@ -123,36 +123,40 @@
-- Standard library
library IEEE;
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
use IEEE.STD_LOGIC_1164.all; -- std_logic definitions
use IEEE.NUMERIC_STD.all; -- conversion functions-- Specific library
-- Specific library
library work;
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
use work.tdc_core_pkg.all; -- definitions of types, constants, entities
library unisim;
use unisim.vcomponents.all;
--=================================================================================================
-- Entity declaration for start_retrig_ctrl
--=================================================================================================
entity start_retrig_ctrl is
generic
(g_width : integer := 32);
port
-- INPUTS
-- Signal from the clk_rst_manager
(clk_i : in std_logic;
rst_i : in std_logic;
-- INPUTS
-- Signal from the clk_rst_manager
(clk_i : in std_logic;
rst_i : in std_logic;
-- Signal from the acam_timecontrol_interface
acam_intflag_f_edge_p_i : in std_logic;
int_flag_i : in std_logic;
r_int_flag_dly_rst_i : in std_logic;
r_int_flag_dly_inc_i : in std_logic;
r_int_flag_dly_ce_i : in std_logic;
-- Signal from the one_hz_generator unit
utc_p_i : in std_logic;
-- OUTPUTS
utc_p_i : in std_logic;
-- OUTPUTS
-- Signals to the data_formatting unit
current_retrig_nb_o : out std_logic_vector(g_width-1 downto 0);
current_retrig_nb_o : out std_logic_vector(31 downto 0);
roll_over_incr_recent_o : out std_logic;
clk_i_cycles_offset_o : out std_logic_vector(g_width-1 downto 0);
roll_over_nb_o : out std_logic_vector(g_width-1 downto 0);
retrig_nb_offset_o : out std_logic_vector(g_width-1 downto 0));
clk_i_cycles_offset_o : out std_logic_vector(31 downto 0);
roll_over_nb_o : out std_logic_vector(31 downto 0);
retrig_nb_offset_o : out std_logic_vector(31 downto 0));
end start_retrig_ctrl;
......@@ -163,13 +167,14 @@ end start_retrig_ctrl;
architecture rtl of start_retrig_ctrl is
signal clk_i_cycles_offset : std_logic_vector(g_width-1 downto 0);
signal current_cycles : std_logic_vector(g_width-1 downto 0);
signal current_retrig_nb : std_logic_vector(g_width-1 downto 0);
signal retrig_nb_offset : std_logic_vector(g_width-1 downto 0);
signal clk_i_cycles_offset : std_logic_vector(31 downto 0);
signal current_cycles : std_logic_vector(31 downto 0);
signal current_retrig_nb : std_logic_vector(31 downto 0);
signal retrig_nb_offset : std_logic_vector(31 downto 0);
signal retrig_p : std_logic;
signal roll_over_c : unsigned(g_width-1 downto 0);
signal roll_over_c : unsigned(31 downto 0);
signal int_flag_stb_p, int_flag_dly, int_flag, int_flag_d, int_flag_p : std_logic;
--=================================================================================================
-- architecture begin
......@@ -233,46 +238,94 @@ begin
-- These two counters keep a track of the current internal start retrigger
-- of the ACAM in parallel with the ACAM itself. Counting up to c_ACAM_RETRIG_PERIOD = 64
retrig_period_counter: free_counter -- retrigger periods
generic map
(width => g_width)
port map
(clk_i => clk_i,
rst_i => acam_intflag_f_edge_p_i,
counter_en_i => '1',
counter_top_i => c_ACAM_RETRIG_PERIOD,
-------------------------------------------
counter_is_zero_o => retrig_p,
counter_o => current_cycles);
-------------------------------------------
retrig_nb_counter: incr_counter -- number of retriggers counting from 0 to 255 and restarting
generic map -- through the acam_intflag_f_edge_p_i
(width => g_width)
iodelay2_bus : IODELAY2
generic map (
DATA_RATE => "SDR",
IDELAY_VALUE => 0,
IDELAY_TYPE => "VARIABLE_FROM_ZERO",
COUNTER_WRAPAROUND => "STAY_AT_LIMIT",
DELAY_SRC => "IDATAIN",
SERDES_MODE => "NONE",
SIM_TAPDELAY_VALUE => 75)
port map (
-- required datapath
IDATAIN => int_flag_i,
DATAOUT => int_flag_dly,
T => '1',
-- inactive data connections
DATAOUT2 => open,
DOUT => open,
ODATAIN => '0',
TOUT => open,
-- connect up the clocks
IOCLK0 => clk_i, -- High speed clock for calibration for SDR/DDR
IOCLK1 => '0', -- High speed clock for calibration for DDR
CLK => clk_i,
CAL => '0',
INC => r_int_flag_dly_inc_i,
CE => r_int_flag_dly_ce_i,
BUSY => open,
RST => r_int_flag_dly_rst_i);
p_sample_int_flag : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_i = '1' then
int_flag_d <= '0';
int_flag <= '0';
else
int_flag <= int_flag_dly;
int_flag_d <= int_flag;
end if;
end if;
end process;
int_flag_p <= not int_flag and int_flag_d;
retrig_period_counter : free_counter -- retrigger periods
generic map
(width => 32)
port map
(clk_i => clk_i,
rst_i => acam_intflag_f_edge_p_i,
counter_top_i => x"00000100",
counter_incr_en_i => retrig_p,
counter_is_full_o => open,
(clk_i => clk_i,
rst_i => int_flag_p,
counter_en_i => '1',
counter_top_i => c_ACAM_RETRIG_PERIOD,
-------------------------------------------
counter_o => current_retrig_nb);
counter_is_zero_o => retrig_p,
counter_o => current_cycles);
-------------------------------------------
retrig_nb_counter : incr_counter -- number of retriggers counting from 0 to 255 and restarting
generic map -- through the acam_intflag_f_edge_p_i
(width => 32)
port map
(clk_i => clk_i,
rst_i => int_flag_p,
counter_top_i => x"00000100",
counter_incr_en_i => retrig_p,
counter_is_full_o => open,
-------------------------------------------
counter_o => current_retrig_nb);
-------------------------------------------
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- This counter keeps track of the number of overflows of the ACAM counter within one second
roll_over_counter: process (clk_i)
roll_over_counter : process (clk_i)
begin
if rising_edge (clk_i) then
if utc_p_i = '1' and acam_intflag_f_edge_p_i = '0' then
roll_over_c <= x"00000000";
-- the following case covers the rare possibility when utc_p_i and acam_intflag_f_edge_p_i
-- arrive on the exact same moment
elsif utc_p_i = '1' and acam_intflag_f_edge_p_i = '1' then
roll_over_c <= x"00000001";
elsif acam_intflag_f_edge_p_i = '1' then
if utc_p_i = '1' and int_flag_p = '0' then
roll_over_c <= x"00000000";
-- the following case covers the rare possibility when utc_p_i and acam_intflag_f_edge_p_i
-- arrive on the exact same moment
elsif utc_p_i = '1' and int_flag_p = '1' then
roll_over_c <= x"00000001";
elsif int_flag_p = '1' then
roll_over_c <= roll_over_c + "1";
end if;
end if;
......@@ -282,12 +335,12 @@ begin
-- When a new second starts, all values are captured and stored as offsets.
-- when a timestamp arrives, these offsets will be subtracted in order
-- to base the final timestamp with respect to the current second.
capture_offset: process (clk_i)
capture_offset : process (clk_i)
begin
if rising_edge (clk_i) then
if rst_i ='1' then
clk_i_cycles_offset <= (others=>'0');
retrig_nb_offset <= (others=>'0');
if rst_i = '1' then
clk_i_cycles_offset <= (others => '0');
retrig_nb_offset <= (others => '0');
elsif utc_p_i = '1' then
clk_i_cycles_offset <= current_cycles;
......@@ -302,7 +355,7 @@ begin
clk_i_cycles_offset_o <= clk_i_cycles_offset;
retrig_nb_offset_o <= retrig_nb_offset;
roll_over_nb_o <= std_logic_vector(roll_over_c);
current_retrig_nb_o <= current_retrig_nb; -- for debug
current_retrig_nb_o <= current_retrig_nb; -- for debug
end architecture rtl;
......@@ -312,4 +365,4 @@ end architecture rtl;
--=================================================================================================
---------------------------------------------------------------------------------------------------
-- E N D O F F I L E
---------------------------------------------------------------------------------------------------
\ No newline at end of file
---------------------------------------------------------------------------------------------------
hdl/rtl/tdc_buffer_control_regs.vhd 0 → 100644
View file @ 8cb00631
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Buffer Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_buffer_control_regs.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_buffer_control_regs.wb
-- Created : Mon Aug 6 23:30:18 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_buffer_control_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.TDC_BUF_wbgen2_pkg.all;
entity tdc_buffer_control_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDC_BUF_in_registers;
regs_o : out t_TDC_BUF_out_registers
);
end tdc_buffer_control_wb;
architecture syn of tdc_buffer_control_wb is
signal tdc_buf_csr_enable_int : std_logic ;
signal tdc_buf_csr_irq_timeout_int : std_logic_vector(9 downto 0);
signal tdc_buf_csr_burst_size_int : std_logic_vector(9 downto 0);
signal tdc_buf_csr_switch_buffers_dly0 : std_logic ;
signal tdc_buf_csr_switch_buffers_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tdc_buf_csr_enable_int <= '0';
tdc_buf_csr_irq_timeout_int <= "0000000000";
tdc_buf_csr_burst_size_int <= "0000000000";
tdc_buf_csr_switch_buffers_int <= '0';
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tdc_buf_csr_switch_buffers_int <= '0';
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.tdc_buf_csr_done_load_o <= '0';
regs_o.tdc_buf_csr_overflow_load_o <= '0';
regs_o.tdc_buf_cur_base_load_o <= '0';
regs_o.tdc_buf_cur_size_size_load_o <= '0';
regs_o.tdc_buf_cur_size_valid_load_o <= '0';
regs_o.tdc_buf_next_base_load_o <= '0';
regs_o.tdc_buf_next_size_size_load_o <= '0';
regs_o.tdc_buf_next_size_valid_load_o <= '0';
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (slave_i.we = '1') then
tdc_buf_csr_enable_int <= wrdata_reg(0);
tdc_buf_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
tdc_buf_csr_burst_size_int <= wrdata_reg(20 downto 11);
tdc_buf_csr_switch_buffers_int <= wrdata_reg(21);
regs_o.tdc_buf_csr_done_load_o <= '1';
regs_o.tdc_buf_csr_overflow_load_o <= '1';
end if;
rddata_reg(0) <= tdc_buf_csr_enable_int;
rddata_reg(10 downto 1) <= tdc_buf_csr_irq_timeout_int;
rddata_reg(20 downto 11) <= tdc_buf_csr_burst_size_int;
rddata_reg(21) <= '0';
rddata_reg(22) <= regs_i.tdc_buf_csr_done_i;
rddata_reg(23) <= regs_i.tdc_buf_csr_overflow_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_cur_size_size_load_o <= '1';
regs_o.tdc_buf_cur_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdc_buf_cur_size_size_i;
rddata_reg(30) <= regs_i.tdc_buf_cur_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdc_buf_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (slave_i.we = '1') then
regs_o.tdc_buf_next_size_size_load_o <= '1';
regs_o.tdc_buf_next_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdc_buf_next_size_size_i;
rddata_reg(30) <= regs_i.tdc_buf_next_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Enable acquisition
regs_o.tdc_buf_csr_enable_o <= tdc_buf_csr_enable_int;
-- IRQ Timeout (ms)
regs_o.tdc_buf_csr_irq_timeout_o <= tdc_buf_csr_irq_timeout_int;
-- Burst size (timestamps)
regs_o.tdc_buf_csr_burst_size_o <= tdc_buf_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdc_buf_csr_switch_buffers_dly0 <= '0';
regs_o.tdc_buf_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
tdc_buf_csr_switch_buffers_dly0 <= tdc_buf_csr_switch_buffers_int;
regs_o.tdc_buf_csr_switch_buffers_o <= tdc_buf_csr_switch_buffers_int and (not tdc_buf_csr_switch_buffers_dly0);
end if;
end process;
-- Burst complete
regs_o.tdc_buf_csr_done_o <= wrdata_reg(22);
-- DMA overflow
regs_o.tdc_buf_csr_overflow_o <= wrdata_reg(23);
-- Base address
regs_o.tdc_buf_cur_base_o <= wrdata_reg(31 downto 0);
-- Number of data samples
-- Size
regs_o.tdc_buf_cur_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdc_buf_cur_size_valid_o <= wrdata_reg(30);
-- Base address
regs_o.tdc_buf_next_base_o <= wrdata_reg(31 downto 0);
-- Size (in transfers)
regs_o.tdc_buf_next_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdc_buf_next_size_valid_o <= wrdata_reg(30);
rwaddr_reg <= slave_i.adr(4 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
hdl/rtl/tdc_buffer_control_regs_wbgen2_pkg.vhd 0 → 100644
View file @ 8cb00631
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Buffer Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_buffer_control_regs_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_buffer_control_regs.wb
-- Created : Mon Aug 6 23:30:18 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_buffer_control_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDC_BUF_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDC_BUF_in_registers is record
tdc_buf_csr_done_i : std_logic;
tdc_buf_csr_overflow_i : std_logic;
tdc_buf_cur_base_i : std_logic_vector(31 downto 0);
tdc_buf_cur_count_i : std_logic_vector(31 downto 0);
tdc_buf_cur_size_size_i : std_logic_vector(29 downto 0);
tdc_buf_cur_size_valid_i : std_logic;
tdc_buf_next_base_i : std_logic_vector(31 downto 0);
tdc_buf_next_size_size_i : std_logic_vector(29 downto 0);
tdc_buf_next_size_valid_i : std_logic;
end record;
constant c_TDC_BUF_in_registers_init_value: t_TDC_BUF_in_registers := (
tdc_buf_csr_done_i => '0',
tdc_buf_csr_overflow_i => '0',
tdc_buf_cur_base_i => (others => '0'),
tdc_buf_cur_count_i => (others => '0'),
tdc_buf_cur_size_size_i => (others => '0'),
tdc_buf_cur_size_valid_i => '0',
tdc_buf_next_base_i => (others => '0'),
tdc_buf_next_size_size_i => (others => '0'),
tdc_buf_next_size_valid_i => '0'
);
-- Output registers (WB slave -> user design)
type t_TDC_BUF_out_registers is record
tdc_buf_csr_enable_o : std_logic;
tdc_buf_csr_irq_timeout_o : std_logic_vector(9 downto 0);
tdc_buf_csr_burst_size_o : std_logic_vector(9 downto 0);
tdc_buf_csr_switch_buffers_o : std_logic;
tdc_buf_csr_done_o : std_logic;
tdc_buf_csr_done_load_o : std_logic;
tdc_buf_csr_overflow_o : std_logic;
tdc_buf_csr_overflow_load_o : std_logic;
tdc_buf_cur_base_o : std_logic_vector(31 downto 0);
tdc_buf_cur_base_load_o : std_logic;
tdc_buf_cur_size_size_o : std_logic_vector(29 downto 0);
tdc_buf_cur_size_size_load_o : std_logic;
tdc_buf_cur_size_valid_o : std_logic;
tdc_buf_cur_size_valid_load_o : std_logic;
tdc_buf_next_base_o : std_logic_vector(31 downto 0);
tdc_buf_next_base_load_o : std_logic;
tdc_buf_next_size_size_o : std_logic_vector(29 downto 0);
tdc_buf_next_size_size_load_o : std_logic;
tdc_buf_next_size_valid_o : std_logic;
tdc_buf_next_size_valid_load_o : std_logic;
end record;
constant c_TDC_BUF_out_registers_init_value: t_TDC_BUF_out_registers := (
tdc_buf_csr_enable_o => '0',
tdc_buf_csr_irq_timeout_o => (others => '0'),
tdc_buf_csr_burst_size_o => (others => '0'),
tdc_buf_csr_switch_buffers_o => '0',
tdc_buf_csr_done_o => '0',
tdc_buf_csr_done_load_o => '0',
tdc_buf_csr_overflow_o => '0',
tdc_buf_csr_overflow_load_o => '0',
tdc_buf_cur_base_o => (others => '0'),
tdc_buf_cur_base_load_o => '0',
tdc_buf_cur_size_size_o => (others => '0'),
tdc_buf_cur_size_size_load_o => '0',
tdc_buf_cur_size_valid_o => '0',
tdc_buf_cur_size_valid_load_o => '0',
tdc_buf_next_base_o => (others => '0'),
tdc_buf_next_base_load_o => '0',
tdc_buf_next_size_size_o => (others => '0'),
tdc_buf_next_size_size_load_o => '0',
tdc_buf_next_size_valid_o => '0',
tdc_buf_next_size_valid_load_o => '0'
);
function "or" (left, right: t_TDC_BUF_in_registers) return t_TDC_BUF_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_buffer_control_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDC_BUF_in_registers;
regs_o : out t_TDC_BUF_out_registers
);
end component;
end package;
package body TDC_BUF_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_TDC_BUF_in_registers) return t_TDC_BUF_in_registers is
variable tmp: t_TDC_BUF_in_registers;
begin
tmp.tdc_buf_csr_done_i := f_x_to_zero(left.tdc_buf_csr_done_i) or f_x_to_zero(right.tdc_buf_csr_done_i);
tmp.tdc_buf_csr_overflow_i := f_x_to_zero(left.tdc_buf_csr_overflow_i) or f_x_to_zero(right.tdc_buf_csr_overflow_i);
tmp.tdc_buf_cur_base_i := f_x_to_zero(left.tdc_buf_cur_base_i) or f_x_to_zero(right.tdc_buf_cur_base_i);
tmp.tdc_buf_cur_count_i := f_x_to_zero(left.tdc_buf_cur_count_i) or f_x_to_zero(right.tdc_buf_cur_count_i);
tmp.tdc_buf_cur_size_size_i := f_x_to_zero(left.tdc_buf_cur_size_size_i) or f_x_to_zero(right.tdc_buf_cur_size_size_i);
tmp.tdc_buf_cur_size_valid_i := f_x_to_zero(left.tdc_buf_cur_size_valid_i) or f_x_to_zero(right.tdc_buf_cur_size_valid_i);
tmp.tdc_buf_next_base_i := f_x_to_zero(left.tdc_buf_next_base_i) or f_x_to_zero(right.tdc_buf_next_base_i);
tmp.tdc_buf_next_size_size_i := f_x_to_zero(left.tdc_buf_next_size_size_i) or f_x_to_zero(right.tdc_buf_next_size_size_i);
tmp.tdc_buf_next_size_valid_i := f_x_to_zero(left.tdc_buf_next_size_valid_i) or f_x_to_zero(right.tdc_buf_next_size_valid_i);
return tmp;
end function;
end package body;
hdl/rtl/tdc_core_pkg.vhd
View file @ 8cb00631
This diff is collapsed.
hdl/rtl/tdc_dma_channel.vhd 0 → 100644
View file @ 8cb00631
This diff is collapsed.
hdl/rtl/tdc_dma_channel_regs.vhd 0 → 100644
View file @ 8cb00631
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC DMA Channel Control Registers
---------------------------------------------------------------------------------------
-- File : tdc_dma_channel_regs.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_dma_channel_regs.wb
-- Created : Wed Jul 18 23:25:00 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_dma_channel_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.TDMA_wbgen2_pkg.all;
entity tdc_dma_channel_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDMA_in_registers;
regs_o : out t_TDMA_out_registers
);
end tdc_dma_channel_wb;
architecture syn of tdc_dma_channel_wb is
signal tdma_csr_enable_int : std_logic ;
signal tdma_csr_irq_timeout_int : std_logic_vector(9 downto 0);
signal tdma_csr_burst_size_int : std_logic_vector(9 downto 0);
signal tdma_csr_switch_buffers_dly0 : std_logic ;
signal tdma_csr_switch_buffers_int : std_logic ;
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments
wrdata_reg <= slave_i.dat;
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
tdma_csr_enable_int <= '0';
tdma_csr_irq_timeout_int <= "0000000000";
tdma_csr_burst_size_int <= "0000000000";
tdma_csr_switch_buffers_int <= '0';
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
tdma_csr_switch_buffers_int <= '0';
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
ack_in_progress <= '0';
else
regs_o.tdma_csr_done_load_o <= '0';
regs_o.tdma_csr_overflow_load_o <= '0';
regs_o.tdma_cur_base_load_o <= '0';
regs_o.tdma_cur_size_size_load_o <= '0';
regs_o.tdma_cur_size_valid_load_o <= '0';
regs_o.tdma_next_base_load_o <= '0';
regs_o.tdma_next_size_size_load_o <= '0';
regs_o.tdma_next_size_valid_load_o <= '0';
end if;
else
if ((slave_i.cyc = '1') and (slave_i.stb = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (slave_i.we = '1') then
tdma_csr_enable_int <= wrdata_reg(0);
tdma_csr_irq_timeout_int <= wrdata_reg(10 downto 1);
tdma_csr_burst_size_int <= wrdata_reg(20 downto 11);
tdma_csr_switch_buffers_int <= wrdata_reg(21);
regs_o.tdma_csr_done_load_o <= '1';
regs_o.tdma_csr_overflow_load_o <= '1';
end if;
rddata_reg(0) <= tdma_csr_enable_int;
rddata_reg(10 downto 1) <= tdma_csr_irq_timeout_int;
rddata_reg(20 downto 11) <= tdma_csr_burst_size_int;
rddata_reg(21) <= '0';
rddata_reg(22) <= regs_i.tdma_csr_done_i;
rddata_reg(23) <= regs_i.tdma_csr_overflow_i;
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(2) <= '1';
ack_in_progress <= '1';
when "001" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (slave_i.we = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_cur_count_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (slave_i.we = '1') then
regs_o.tdma_cur_size_size_load_o <= '1';
regs_o.tdma_cur_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdma_cur_size_size_i;
rddata_reg(30) <= regs_i.tdma_cur_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (slave_i.we = '1') then
regs_o.tdma_next_base_load_o <= '1';
end if;
rddata_reg(31 downto 0) <= regs_i.tdma_next_base_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (slave_i.we = '1') then
regs_o.tdma_next_size_size_load_o <= '1';
regs_o.tdma_next_size_valid_load_o <= '1';
end if;
rddata_reg(29 downto 0) <= regs_i.tdma_next_size_size_i;
rddata_reg(30) <= regs_i.tdma_next_size_valid_i;
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
slave_o.dat <= rddata_reg;
-- Enable DMA
regs_o.tdma_csr_enable_o <= tdma_csr_enable_int;
-- IRQ Timeout (ms)
regs_o.tdma_csr_irq_timeout_o <= tdma_csr_irq_timeout_int;
-- Burst size (timestamps)
regs_o.tdma_csr_burst_size_o <= tdma_csr_burst_size_int;
-- Switch buffers
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
tdma_csr_switch_buffers_dly0 <= '0';
regs_o.tdma_csr_switch_buffers_o <= '0';
elsif rising_edge(clk_sys_i) then
tdma_csr_switch_buffers_dly0 <= tdma_csr_switch_buffers_int;
regs_o.tdma_csr_switch_buffers_o <= tdma_csr_switch_buffers_int and (not tdma_csr_switch_buffers_dly0);
end if;
end process;
-- DMA complete
regs_o.tdma_csr_done_o <= wrdata_reg(22);
-- DMA overflow
regs_o.tdma_csr_overflow_o <= wrdata_reg(23);
-- Base address
regs_o.tdma_cur_base_o <= wrdata_reg(31 downto 0);
-- Number of data samples in the buffer
-- Size (in transfers)
regs_o.tdma_cur_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdma_cur_size_valid_o <= wrdata_reg(30);
-- Base address
regs_o.tdma_next_base_o <= wrdata_reg(31 downto 0);
-- Size (in transfers)
regs_o.tdma_next_size_size_o <= wrdata_reg(29 downto 0);
-- Valid flag
regs_o.tdma_next_size_valid_o <= wrdata_reg(30);
rwaddr_reg <= slave_i.adr(4 downto 2);
slave_o.stall <= (not ack_sreg(0)) and (slave_i.stb and slave_i.cyc);
slave_o.err <= '0';
slave_o.rty <= '0';
-- ACK signal generation. Just pass the LSB of ACK counter.
slave_o.ack <= ack_sreg(0);
end syn;
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hdl/rtl/tdc_onewire_wbgen2_pkg.vhd 0 → 100644
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---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for TDC Onewire Master
---------------------------------------------------------------------------------------
-- File : tdc_onewire_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from wbgen/tdc_onewire_wb.wb
-- Created : Tue Sep 11 11:16:49 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wbgen/tdc_onewire_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package TDC_OW_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_TDC_OW_in_registers is record
tdc_ow_csr_valid_i : std_logic;
tdc_ow_temp_i : std_logic_vector(15 downto 0);
tdc_ow_id_h_i : std_logic_vector(31 downto 0);
tdc_ow_id_l_i : std_logic_vector(31 downto 0);
end record;
constant c_TDC_OW_in_registers_init_value: t_TDC_OW_in_registers := (
tdc_ow_csr_valid_i => '0',
tdc_ow_temp_i => (others => '0'),
tdc_ow_id_h_i => (others => '0'),
tdc_ow_id_l_i => (others => '0')
);
-- Output registers (WB slave -> user design)
type t_TDC_OW_out_registers is record
tdc_ow_csr_valid_o : std_logic;
tdc_ow_csr_valid_load_o : std_logic;
end record;
constant c_TDC_OW_out_registers_init_value: t_TDC_OW_out_registers := (
tdc_ow_csr_valid_o => '0',
tdc_ow_csr_valid_load_o => '0'
);
function "or" (left, right: t_TDC_OW_in_registers) return t_TDC_OW_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
component tdc_onewire_wb is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
int_o : out std_logic;
regs_i : in t_TDC_OW_in_registers;
regs_o : out t_TDC_OW_out_registers
);
end component;
end package;
package body TDC_OW_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if x = '1' then
return '1';
else
return '0';
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_TDC_OW_in_registers) return t_TDC_OW_in_registers is
variable tmp: t_TDC_OW_in_registers;
begin
tmp.tdc_ow_csr_valid_i := f_x_to_zero(left.tdc_ow_csr_valid_i) or f_x_to_zero(right.tdc_ow_csr_valid_i);
tmp.tdc_ow_temp_i := f_x_to_zero(left.tdc_ow_temp_i) or f_x_to_zero(right.tdc_ow_temp_i);
tmp.tdc_ow_id_h_i := f_x_to_zero(left.tdc_ow_id_h_i) or f_x_to_zero(right.tdc_ow_id_h_i);
tmp.tdc_ow_id_l_i := f_x_to_zero(left.tdc_ow_id_l_i) or f_x_to_zero(right.tdc_ow_id_l_i);
return tmp;
end function;
end package body;
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hdl/syn/spec/Manifest.py
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......@@ -12,3 +12,4 @@ syn_tool = "ise"
top_module = "wr_spec_tdc"
modules = { "local" : [ "../../top/spec" ] }
ctrls = ["bank3_32b_32b"]
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hdl/top/spec/Manifest.py
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......@@ -9,10 +9,8 @@ modules = {
"../../ip_cores/gn4124-core",
"../../ip_cores/general-cores",
"../../ip_cores/wr-cores",
"../../ip_cores/wr-cores/board/spec"
],
"git" : [
"git://ohwr.org/hdl-core-lib/etherbone-core.git",
],
"../../ip_cores/wr-cores/board/spec",
"../../ip_cores/ddr3-sp6-core"
]
}
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