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Dimitris Lampridis authoredThe following changes were done: 1. Point all submodules to new OHWR 2. update ddr3-sp6-core to latest master because the previous commit (8618c1e154c322be34cb069b62d8293527744dda) was not available in OHWR. Please test! 3. remove etherbone-core 4. update general-cores to latest master and use the updated gc_ds182x_readout module
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