hdl: change TEST1 register layout

d0dc3163 · Tomasz Wlostowski · a388eab5 · d0dc3163
Commit d0dc3163 authored Sep 21, 2018 by Tomasz Wlostowski
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Showing with 4 additions and 16 deletions

reg_ctrl.vhd hdl/rtl/reg_ctrl.vhd +4 -16

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--- a/hdl/rtl/reg_ctrl.vhd
+++ b/hdl/rtl/reg_ctrl.vhd
@@ -153,9 +153,7 @@ entity reg_ctrl is
      -- Signal to the acam_timecontrol_interface unit -- eva: i think it s not needed
      start_phase_o : out std_logic_vector(g_width-1 downto 0);

-      int_flag_dly_ce_o : out std_logic;
-      int_flag_dly_inc_o : out std_logic;
-      int_flag_dly_rst_o : out std_logic
+      int_flag_delay_o : out std_logic_vector(15 downto 0)
      );

 end reg_ctrl;
@@ -363,13 +361,9 @@ begin
        dac_word             <= c_DEFAULT_DAC_WORD;  -- default DAC Vout = 1.65

        gen_fake_ts_enable_o <= '0';
-
-        int_flag_dly_rst_o <= '0';
-        int_flag_dly_ce_o <= '0';
-        int_flag_dly_inc_o <= '0';
-        cyc2_in_progress <= '0';
+        int_flag_delay_o <= (others => '0');
+        
      elsif wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
-        cyc2_in_progress <= '1';
        
        
        if reg_adr = c_STARTING_UTC_ADR then
@@ -410,17 +404,11 @@ begin
          gen_fake_ts_period_o <= wb_in.dat(27 downto 0);
        end if;

-        int_flag_dly_ce_o <= '0';
        
        if reg_adr = c_TEST1_ADR then
-          int_flag_dly_ce_o <= wb_in.dat(0) and not cyc2_in_progress;
-          int_flag_dly_inc_o <= wb_in.dat(1);
-          int_flag_dly_rst_o <= wb_in.dat(2);
+          int_flag_delay_o <= wb_in.dat(15 downto 0);
        end if;

-      else
-        int_flag_dly_ce_o <= '0';
-        cyc2_in_progress <= '0';
      end if;
    end if;
  end process;