[hdl] [bugfix] Fix overflow/underflow check in timestamp adder/subtractor

7b243fd4 · Dimitris Lampridis · 84ffc99f · 7b243fd4
Commit 7b243fd4 authored Sep 26, 2019 by Dimitris Lampridis
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tdc_ts_addsub.vhd hdl/rtl/tdc_ts_addsub.vhd +3 -3

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--- a/hdl/rtl/tdc_ts_addsub.vhd
+++ b/hdl/rtl/tdc_ts_addsub.vhd
@@ -6,7 +6,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-08-29
-- Last update: 2018-09-10
+-- Last update: 2019-09-26
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -169,9 +169,9 @@ begin  -- rtl
          unf_coarse <= "00";
        end if;

-        if ( sums(1).coarse >= g_frac_range ) then
+        if ( sums(1).coarse >= g_coarse_range ) then
          ovf_coarse <= "10";
-        elsif ( sums(1).coarse >= 2*g_frac_range ) then
+        elsif ( sums(1).coarse >= 2*g_coarse_range ) then
          ovf_coarse <= "01";
        else
          ovf_coarse <= "00";