- 11 Sep, 2015 5 commits
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David Cussans authored
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David Cussans authored
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David Cussans authored
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David Cussans authored
Infieri summer school
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David Cussans authored
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- 03 Sep, 2015 3 commits
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David Cussans authored
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David Cussans authored
Added Dummy_DUT.vhd - which clocks out trigger number Added delay.vhd , dtype.vhd ( used by DUTInterface_EUDET_rtl.vhd ) Edited comments in DUTInterface_EUDET_rtl.vhd Wrote test bench which instantiates dummy EUDET DUTs ( fmc-tlu_v0-1_eudet_test-bench.vhd , based on fmc-tlu_v0-1_test-bench.vhd ) Created spread-sheet to keep track of verification tests on firmware. Wrote script to put DUTs into AIDA mode ( test_aida_tlu_internal_triggers_eudet_v2.py , based on test_aida_tlu_internal_triggers_v2.py )
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David Cussans authored
Write to "DUTInterfaceMode" register to choose between EUDET (0) and AIDA (1) modes Will result in pseudo-LVDS for clock lines ( Boo.... ) put termination resistors in bodge boards. Executes in simulation, produces internal triggers when test_aida_tlu_internal_triggers_v2.py run. Edited setup_project.tcl so that new files are inserted into ISE project ( NOT TESTED) Edited add_files.tcl so that new files are are inserted into Modelsim/Questa project ( NOT TESTED) Removed unused trigger_counter_o port from EventFormatter. Connected up DUTInterface to TriggerLogic trigger_counter instead.
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- 02 Sep, 2015 2 commits
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David Cussans authored
Factorized hdl/common/DUTInterfaces_rtl.vhd to put hand-shake specific ( EUDET/AIDA ) code into hdl/common/DUTInterface_AIDA_rtl.vhd and hdl/common/DUTInterface_EUDET_rtl.vhd. N.B. DUTInterface_EUDET_rtl.vhd not yet tested. DUTInterface_AIDA_rtl.vhd runs in simulation. Improved Doxygen comments in coincidenceLogic_rtl.vhd , hdl/common/synchronizeRegisters_rtl.vhd , hdl/common/triggerLogic_rtl.vhd Increased number of DUTs in simulation_src/fmc-tlu_v0-1_test-bench.vhd from 2 to 3. Modified
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David Cussans authored
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- 01 Sep, 2015 1 commit
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David Cussans authored
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- 28 Aug, 2015 1 commit
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David Cussans authored
* Fixed bug in simulation by connecting up 40MHz clock from clock_sim module in IPBusInterface * By-passed problem in test_aida_tlu_internal_triggers_v2.py by setting thresholds to -0.2V so that triggers not active
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- 27 Aug, 2015 2 commits
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David Cussans authored
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David Cussans authored
* Editing simulation test bench to remove ports no longer present ( simulation_src/fmc-tlu_v0-1_test-bench.vhd ) * Tidying up documentation ( in Doxygen / VHDL need to put @brief etc. near entity decl not at top of file ... )
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- 26 Aug, 2015 3 commits
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David Cussans authored
T0_Shutter_Iface_rtl.vhd (which doesn't expect external shutter/T0 signals) * Edited setup_project.tcl to reflect change from TPx3_iface_rtl.vhd --> T0_Shutter_Iface_rtl.vhd * Edited sp605_FMC_mTLU_v1a.ucf to reflect change from TPx3_iface_rtl.vhd --> T0_Shutter_Iface_rtl.vhd * Edited fmc_tlu_chipscope.cdc to change connections associated with change from TPx3_iface_rtl.vhd --> T0_Shutter_Iface_rtl.vhd
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David Cussans authored
to internal clock generation before merging back to trunk.
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David Cussans authored
Made links from HDL source files to HDL designer directories to permit HDL designer to work but make is easy to build firmware if HDL designer not present Added some more scripts.
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- 24 Aug, 2015 1 commit
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David Cussans authored
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- 28 May, 2015 4 commits
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David Cussans authored
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David Cussans authored
Adding files to build scripts
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David Cussans authored
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David Cussans authored
* Edited top_extphy to include IPBus interface to TPx3 interface.
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- 21 May, 2015 3 commits
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David Cussans authored
* Set top module by hand. * Changed UCF to be hacked-for-telescope version * Removed unnessary files that were being added to project * Added clock_sim.vhd , eth_mac_sim.vhd. The "generate" statement will stop them being synthesized but they still need to be in project to avoid errors.
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David Cussans authored
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David Cussans authored
Added a common delay to all pulses ( needs changing ). Edited triggerlogic to accomodate this. * Moved s_reset_timestamp_ipbus<='0' , might have been causing a bug in reset * Edited TPix3_iface to allow the shutter and T0 to be set under IPBus control * logic_clocks now chooses between external ( from 2-pole Lemo ) and internal ( from sysclk xtal ) clock using a generate statement and generic. * DUTInterfaces - stretch output trigger pulse to two clock cycles.
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- 15 May, 2015 6 commits
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David Cussans authored
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David Cussans authored
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David Cussans authored
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David Cussans authored
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David Cussans authored
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David Cussans authored
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- 13 May, 2015 1 commit
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David Cussans authored
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- 11 May, 2015 3 commits
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David Cussans authored
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David Cussans authored
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David Cussans authored
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- 08 May, 2015 1 commit
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David Cussans authored
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- 09 Dec, 2014 3 commits
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David Cussans authored
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David Cussans authored
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David Cussans authored
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- 05 Dec, 2014 1 commit
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David Cussans authored
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