Fixed bug in clk pin assignment to IBUFDS

d7df40c1 · David Cussans · a2e74625 · d7df40c1
Commit d7df40c1 authored Dec 09, 2014 by David Cussans
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logic_clocks_rtl.vhd firmware/hdl/common/logic_clocks_rtl.vhd +1 -1

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--- a/firmware/hdl/common/logic_clocks_rtl.vhd
+++ b/firmware/hdl/common/logic_clocks_rtl.vhd
@@ -218,7 +218,7 @@ BEGIN
    port map (
      O => s_extclk,  -- Buffer output
      I => extclk_p_b,  -- Diff_p buffer input (connect directly to top-level port)
-      IB => extclk_p_b -- Diff_n buffer input (connect directly to top-level port)
+      IB => extclk_n_b -- Diff_n buffer input (connect directly to top-level port)
      );
  
  ddr_for_extclk_output : ODDR2