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AIDA-2020 TLU
Commit a2fd66ca authored by David Cussans's avatar David Cussans
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Tidying up code

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firmware/chipscope/fmc_tlu_chipscope.cdc
View file @ a2fd66ca
#ChipScope Core Inserter Project File Version 3.0
#Thu Aug 27 14:43:06 BST 2015
Project.device.designInputFile=/users/phdgc/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/top_extphy_cs.ngc
Project.device.designOutputFile=/users/phdgc/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/top_extphy_cs.ngc
#Fri Sep 11 16:26:13 BST 2015
Project.device.designInputFile=/users/phdgc/IPBus_stuff/infieri_summer_school_2015/workspace/Infieri_Lab6_cs.ngc
Project.device.designOutputFile=/users/phdgc/IPBus_stuff/infieri_summer_school_2015/workspace/Infieri_Lab6_cs.ngc
Project.device.deviceFamily=18
Project.device.enableRPMs=true
Project.device.outputDirectory=/users/phdgc/IPBus_stuff/fmc_tlu_test_modify_tpix3_nov14_aug15/workspace/_ngo
Project.device.outputDirectory=/users/phdgc/IPBus_stuff/infieri_summer_school_2015/workspace/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=*veto*
Project.filter<10>=*T0*
Project.filter<11>=T0
Project.filter<12>=I2/s_coarse_timestamp_h*
Project.filter<13>=I2/*ignore*
Project.filter<14>=I2/*coarse_timestamp*
Project.filter<15>=*coarse_timestamp*
Project.filter<16>=*s_coarse_timestamp_h*
Project.filter<17>=*reset_timestamp*
Project.filter<18>=*coarse_timestamp_h*
Project.filter<1>=*busy*
Project.filter<2>=
Project.filter<3>=*external*
Project.filter<4>=*externali*
Project.filter<5>=*veto_i*
Project.filter<6>=*ignore*
Project.filter<7>=*ignore_busy*
Project.filter<8>=I0/*busy*
Project.filter<9>=*shutter*
Project.filter<0>=*gpio*
Project.filter<10>=*veto*
Project.filter<11>=*busy*
Project.filter<12>=*external*
Project.filter<13>=*externali*
Project.filter<14>=*veto_i*
Project.filter<15>=*ignore*
Project.filter<16>=*ignore_busy*
Project.filter<17>=I0/*busy*
Project.filter<18>=*shutter*
Project.filter<1>=*thresh*
Project.filter<2>=*trig*
Project.filter<3>=*thres*
Project.filter<4>=*trigger*
Project.filter<5>=*discr*
Project.filter<6>=trigger*
Project.filter<7>=clk*
Project.filter<8>=clk_*
Project.filter<9>=
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=clk_4x_logic
Project.unit<0>.clockChannel=ClkGen_inst/s_clk160
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=I2/s_coarse_timestamp_h<0>
Project.unit<0>.dataChannel<10>=I0/s_busy_from_dut<2>
Project.unit<0>.dataChannel<11>=I0/veto_o
Project.unit<0>.dataChannel<12>=overall_veto
Project.unit<0>.dataChannel<10>=I3/Mcount_s_post_veto_trigger_counter_cy<2>
Project.unit<0>.dataChannel<11>=I3/Mcount_s_post_veto_trigger_counter_cy<1>
Project.unit<0>.dataChannel<12>=I3/Mcount_s_post_veto_trigger_counter_cy<0>
Project.unit<0>.dataChannel<1>=I2/s_coarse_timestamp_h<1>
Project.unit<0>.dataChannel<2>=I2/s_coarse_timestamp_h<2>
Project.unit<0>.dataChannel<3>=I2/s_coarse_timestamp_h<3>
......@@ -45,27 +45,27 @@ Project.unit<0>.dataChannel<4>=I2/s_reset_timestamp_ipbus
Project.unit<0>.dataChannel<5>=I2/s_reset_timestamp_4x
Project.unit<0>.dataChannel<6>=I10/T0_o
Project.unit<0>.dataChannel<7>=I10/shutter_o
Project.unit<0>.dataChannel<8>=I0/s_busy_from_dut<0>
Project.unit<0>.dataChannel<9>=I0/s_busy_from_dut<1>
Project.unit<0>.dataChannel<8>=I3/s_post_veto_trigger
Project.unit<0>.dataChannel<9>=I3/Mcount_s_post_veto_trigger_counter_cy<3>
Project.unit<0>.dataDepth=2048
Project.unit<0>.dataEqualsTrigger=true
Project.unit<0>.dataPortWidth=13
Project.unit<0>.dataPortWidth=4
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=I2/s_coarse_timestamp_h<0>
Project.unit<0>.triggerChannel<0><0>=gpio_hdr_3_OBUF
Project.unit<0>.triggerChannel<0><10>=I3/Mcount_s_post_veto_trigger_counter_cy<2>
Project.unit<0>.triggerChannel<0><11>=I3/Mcount_s_post_veto_trigger_counter_cy<1>
Project.unit<0>.triggerChannel<0><12>=I3/Mcount_s_post_veto_trigger_counter_cy<0>
Project.unit<0>.triggerChannel<0><1>=I2/s_coarse_timestamp_h<1>
Project.unit<0>.triggerChannel<0><2>=I2/s_coarse_timestamp_h<2>
Project.unit<0>.triggerChannel<0><3>=I2/s_coarse_timestamp_h<3>
Project.unit<0>.triggerChannel<0><4>=I2/s_reset_timestamp_ipbus
Project.unit<0>.triggerChannel<0><5>=I2/s_reset_timestamp_4x
Project.unit<0>.triggerChannel<0><6>=I10/T0_o
Project.unit<0>.triggerChannel<0><7>=I10/shutter_o
Project.unit<0>.triggerChannel<0><1>=gpio_hdr_2_OBUF
Project.unit<0>.triggerChannel<0><2>=gpio_hdr_1_OBUF
Project.unit<0>.triggerChannel<0><3>=gpio_hdr_0_OBUF
Project.unit<0>.triggerChannel<0><4>=threshold_discr_p_i<3>
Project.unit<0>.triggerChannel<0><5>=threshold_discr_p_i<2>
Project.unit<0>.triggerChannel<0><6>=threshold_discr_p_i<1>
Project.unit<0>.triggerChannel<0><7>=threshold_discr_p_i<0>
Project.unit<0>.triggerChannel<0><8>=I3/s_post_veto_trigger
Project.unit<0>.triggerChannel<0><9>=I3/Mcount_s_post_veto_trigger_counter_cy<3>
Project.unit<0>.triggerConditionCountWidth=0
......@@ -74,7 +74,7 @@ Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=5
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=13
Project.unit<0>.triggerPortWidth<0>=4
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
firmware/chipscope/fmc_tlu_chipscope.cpj
View file @ a2fd66ca
This diff is collapsed.
firmware/config/ise14/sp605/coregen.cgp
View file @ a2fd66ca
......@@ -2,8 +2,8 @@ SET busformat = BusFormatAngleBracketNotRipped
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Other
SET flowvendor = Foundation_ISE
SET package = fgg484
SET speedgrade = -3
SET verilogsim = false
SET verilogsim = true
SET vhdlsim = true
firmware/config/ise14/sp605/setup_project.tcl
View file @ a2fd66ca
......@@ -84,16 +84,16 @@ xfile add external/opencores_i2c/i2c_master_top.vhd
# Add TLU cores....
# Add cores for Ethernet
puts "Adding and Regenerating TLU cores"
exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
xfile add ipcore_dir/tlu_event_fifo.xco
xfile add ipcore_dir/FIFO.xco
#puts "Adding and Regenerating TLU cores"
#exec cp fmc-mtlu/firmware/ise/ipcore_dir/tlu_event_fifo.xco ipcore_dir
#exec cp fmc-mtlu/firmware/ise/ipcore_dir/FIFO.xco ipcore_dir
#exec cp fmc-mtlu/firmware/ise/ipcore_dir/CounterUp.xco ipcore_dir
#exec cp fmc-mtlu/firmware/ise/ipcore_dir/internalTriggerGenerator.xco ipcore_dir
#xfile add ipcore_dir/tlu_event_fifo.xco
#xfile add ipcore_dir/FIFO.xco
#xfile add ipcore_dir/CounterUp.xco
xfile add ipcore_dir/internalTriggerGenerator.xco
#xfile add ipcore_dir/internalTriggerGenerator.xco
# Don't regenerate cores for now...
#cd ipcore_dir
......@@ -105,13 +105,7 @@ xfile add ipcore_dir/internalTriggerGenerator.xco
puts "Adding TLU Files "
# Add FMC-MTLU files. First the hand-written VHDL
xfile add fmc-mtlu/firmware/hdl/common/dualSERDES_1to4_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_EUDET_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/single_pulse_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/DUTInterfaces_AIDA_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventBuffer_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/eventFormatter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/i2c_master_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/ipbus_addr_decode.vhd
xfile add fmc-mtlu/firmware/hdl/common/IPBusInterface_rtl.vhd
......@@ -120,28 +114,21 @@ xfile add fmc-mtlu/firmware/hdl/common/logic_clocks_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/Reg_2clks.vhd
#xfile add fmc-mtlu/firmware/hdl/common/registerCounter_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/IODELAYCal_FSM_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/serdes_1_to_n_SDR.vhd
#xfile add fmc-mtlu/firmware/hdl/common/sync_reg.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerInputs_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/triggerLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/clocks_s6_extphy.vhd
xfile add fmc-mtlu/firmware/hdl/common/arrivalTimeLUT_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/test/clock_divider_s6.v
xfile add fmc-mtlu/firmware/hdl/common/counterWithReset_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/synchronizeRegisters_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/handshakes_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/TPx3_iface_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/T0_Shutter_Iface_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/GPP_rtl.vhd
#xfile add fmc-mtlu/firmware/hdl/common/counterDown.vhd
xfile add fmc-mtlu/firmware/hdl/common/pulseClockDomainCrossing_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/coincidenceLogic_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/stretchPulse_rtl.vhd
# Then add the HDL-Designer generated files..
# ( Links to files in HDL designer hierarchy )
xfile add fmc-mtlu/firmware/hdl/miniTLU/top_extphy_struct.vhd
xfile add fmc-mtlu/firmware/hdl/common/Infieri_Lab6_rtl.vhd
xfile add fmc-mtlu/firmware/hdl/common/fmcTLU_pkg_body.vhd
xfile add fmc-mtlu/firmware/hdl/common/fmcTLU_pkg.vhd
......@@ -156,7 +143,7 @@ xfile add fmc-mtlu/firmware/ucf/sp605_FMC_mTLU_v1a.ucf
# Add chipscope definition file.
xfile add fmc-mtlu/firmware/chipscope/fmc_tlu_chipscope.cdc
project set top "top_extphy"
project set top "Infieri_Lab6"
project close
......
firmware/scripts/fmc_tlu_addr_table deleted 100644 → 0
View file @ 6f62ad1c
# Example addr_table file to show the format
#
# num name base addr_width
0 DUTInterfaces 0x020 5
1 triggerInputs 0x040 5
2 triggerLogic 0x060 5
3 eventBuffer 0x080 5
4 logic_clocks 0x0A0 5
5 i2c_master 0x0C0 3
6 Trigger_Generator 0x0E0 5
7 Shutter_Generator 0x100 5
8 Spill_Generator 0x120 5
9 Event_Formatter 0x140 5
10 Handshakes 0x160 5
11 version 0x000 0
firmware/scripts/generate_arrivaltime_lut.py deleted 100644 → 0
View file @ 6f62ad1c
# Look for rising and falling edges in 8-bit vector.
# Print out in form suitable for initializing VHDL array...
# from bitstring import BitArray
firstRisingEdge = []
lastFallingEdge = []
multipleEdgesPresent = []
risingEdgePresent = []
fallingEdgePresent = []
for value in range(0,512):
print hex(value)
# Initialize array and get zero'th element
bitSetArray = []
bitSet = ( 1 & value)
bitSetArray.append(bitSet)
risingEdges = []
fallingEdges = []
for bit in range (1,9):
bitSet = (( 1 << bit ) & value) >> bit
# print bitSet
bitSetArray.append(bitSet)
if (bitSetArray[bit-1] ==0) and (bitSetArray[bit] == 1):
print "Rising edge found"
risingEdges.append(bit)
if (bitSetArray[bit-1] ==1) and (bitSetArray[bit] == 0):
print "Falling edge found"
fallingEdges.append(bit)
if len(risingEdges) != 0:
firstRisingEdge.append(risingEdges[0] - 1)
risingEdgePresent.append(1)
else:
firstRisingEdge.append(0)
risingEdgePresent.append(0)
if len(fallingEdges) != 0:
lastFallingEdge.append(fallingEdges[len(fallingEdges)-1] -1 )
fallingEdgePresent.append(1)
else:
lastFallingEdge.append(0)
fallingEdgePresent.append(0)
if (len(risingEdges) >1 ) or (len(risingEdges) >1 ):
multipleEdgesPresent.append(1)
else:
multipleEdgesPresent.append(0)
print bitSetArray , risingEdges , fallingEdges
print firstRisingEdge
print risingEdgePresent
print
print lastFallingEdge
print fallingEdgePresent
print
print multipleEdgesPresent
# Rising and falling edge times encoded as a LUT. Contents:
# MRFrrrfff
# M = multiple edges present ( more then one rising or falling edge)
# R = at least one rising edge present
# F = at least one falling edge present.
for value in range(0,512):
if not (value % 8):
# print newline every eight values.
print
word = lastFallingEdge[value] + (firstRisingEdge[value]<<3) + (fallingEdgePresent[value]<<6) + (risingEdgePresent[value]<<7) + (multipleEdgesPresent[value]<<8)
# print "last falling edge" , hex(lastFallingEdge[value])
# print "first rising edge" , hex(firstRisingEdge[value])
# print "multi edges?" , multipleEdgesPresent[value]
bitString = ""
for bit in range (0,9):
bitSet = (( 1 << bit ) & word) >> bit
if bitSet:
bitString = "1" + bitString
else:
bitString = "0" + bitString
# print hex(value)
# print hex(word)
print ("\"" + bitString + "\","),
# print
# valBits = BitArray(int = value, length = 8)
# print BitArray
# Find the first rising edge in time and the last falling edge...
firmware/scripts/make_fmc-mtlu_pintest_ise.tcl deleted 100644 → 0
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This diff is collapsed.
firmware/scripts/read_pre_post_veto_triggers.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
numLoops = 1
for iLoop in range(0,numLoops):
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
time.sleep( 1.0 )
firmware/scripts/test_aida_tlu_thresholds.py → firmware/scripts/set_aida_tlu_thresholds.py
View file @ a2fd66ca
......@@ -2,9 +2,11 @@ from PyChipsUser import *
from FmcTluI2c import *
import time
boardIpAddr = "192.168.200.16"
boardIpAddr = "192.168.200.32"
boardPortNum = 50001
print "Connecting to AIDA TLU at ", boardIpAddr
addrTable = AddressTable("./aida_mini_tlu_addr_map.txt")
board = ChipsBusUdp(addrTable, boardIpAddr, boardPortNum)
......@@ -22,18 +24,8 @@ print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
#dacValue = 0x4100
dacValue = 0xFFFF
print "Setting Vthreshold for all DACs. Code = ", dacValue
boardi2c.set_dac(7,dacValue)
time.sleep(2.0)
dacValue = 0x6000
print "Setting Vthreshold for DAC 0. Code = ", dacValue
boardi2c.set_dac(0,dacValue)
time.sleep(2.0)
thresholdVolts = -0.025
print "Setting all thresholds to " , thresholdVolts , " Volts"
print "Voltages on TP14, TP15 , TP16 , TP17\n"
# set DACs to -5mV
boardi2c.set_threshold_voltage(7, -0.05)
boardi2c.set_threshold_voltage(7, thresholdVolts)
firmware/scripts/startTLU.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to setup AIDA TLU for TPix3 telescope <--> TORCH synchronization
#
# David Cussans, December 2012
#
# Nasty hack - use both PyChips and uHAL ( for block read ... )
from PyChipsUser import *
from FmcTluI2c import *
import uhal
import sys
import time
print "Setting up AIDA TLU for TPix3 telescope <--> TORCH synchronization\n"
writeTimestamps = False
listenForTelescopeShutter = True
TriggerInterval = 0 # Units = 160MHz clock ticks.
loopWait = 1.0 # polling interval ( seconds )
pulseDelay = 31 # between 0 and 31 in units of 160MHz clock.
# Point to board in uHAL
manager = uhal.ConnectionManager("file://./connection.xml")
hw = manager.getDevice("minitlu")
device_id = hw.id()
fwVersion = hw.getNode("version").read()
hw.dispatch()
print "Version (uHAL)= " , hex(fwVersion)
# Point to TLU in Pychips
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 2
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
firmwareID=board.read("FirmwareId")
print "Firmware (from PyChips) = " , hex(firmwareID)
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
resetSerdes = 0
# set DACs to -200mV
print "Setting all threshold DAC to -200mV "
boardi2c.set_threshold_voltage(7, -0.2)
clockStatus = board.read("LogicClocksCSR")
print "Clock status ( should be 3 if all clocks locked ) = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
if resetSerdes:
board.write("SerdesRstW", 0x00000003 )
inputStatus = board.read("SerdesRstR")
print "Input status during reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000004 )
inputStatus = board.read("SerdesRstR")
print "Input status during calibration = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after calibration = " , hex(inputStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
board.write("InternalTriggerIntervalW",0)
print "Setting input trigger delay, units = 160MHz clock cycles"
board.write("PulseDelayW",pulseDelay)
pulseDelay = board.read("PulseDelayR")
print "Pulse delay was set to ", pulseDelay
print "Enabling DUT 0 and 1"
board.write("DUTMaskW",3)
DUTMask = board.read("DUTMaskR")
print "DUTMaskR = " , DUTMask
if listenForTelescopeShutter:
print "Listen for veto from shutter"
board.write("IgnoreShutterVetoW",0)
else:
print "Ignore veto from shutter"
board.write("IgnoreShutterVetoW",1)
IgnoreShutterVeto = board.read("IgnoreShutterVetoR")
print "IgnoreShutterVeto = " , IgnoreShutterVeto
print "Ignore veto on DUT 0"
board.write("IgnoreDUTBusyW",1)
IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
print "IgnoreDUTBusyR = " , IgnoreDUTBusy
print "Turning off software trigger veto"
board.write("TriggerVetoW",0)
print "Reseting FIFO"
board.write("EventFifoCSR",0x2)
eventFifoFillLevel = board.read("EventFifoFillLevel")
print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
if writeTimestamps:
print "Enabling data recording"
board.write("Enable_Record_Data",1)
else:
print "Disabling data recording"
board.write("Enable_Record_Data",0)
#print "Enabling handshake: No-handshake"
#board.write("HandshakeTypeW",1)
print "Setting internal trigger interval to " , TriggerInterval , " ( zero = no internal triggers)"
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval
oldEvtNumber = 0
oldPreVetotriggerCount = board.read("PreVetoTriggersR")
oldPostVetotriggerCount = board.read("PostVetoTriggersR")
print "Starting polling loop"
while True:
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
preVetoFreq = (preVetotriggerCount-oldPreVetotriggerCount)/loopWait
postVetoFreq = (postVetotriggerCount-oldPostVetotriggerCount)/loopWait
oldPreVetotriggerCount = preVetotriggerCount
oldPostVetotriggerCount = postVetotriggerCount
print "pre , post veto triggers , pre , post frequency = " , preVetotriggerCount , postVetotriggerCount , preVetoFreq , postVetoFreq
timestampHigh = board.read("CurrentTimestampHR")
timestampLow = board.read("CurrentTimestampLR")
print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
eventFifoFillLevel = board.read("EventFifoFillLevel")
print "FIFO fill level = " , eventFifoFillLevel
#timestampData = board.blockRead("EventFifoData", eventFifoFillLevel)
nEvents = eventFifoFillLevel//4 # only read out whole events ( 4 x 32-bit words )
wordsToRead = nEvents*4
timestampData = hw.getNode("eventBuffer.EventFifoData").readBlock(eventFifoFillLevel)
hw.dispatch()
print "number of events in FIFO = ",nEvents
# print timestampData
for evt in range (0, nEvents-1 ):
lowWord = timestampData[evt*4 + 1] + 0x100000000* timestampData[ (evt*4) + 0] # timestamp
highWord = timestampData[evt*4 + 3] + 0x100000000* timestampData[ (evt*4) + 2] # evt number
evtNumber = timestampData[evt*4 + 3]
if evtNumber != ( oldEvtNumber + 1 ):
print "***WARNING *** Non sqeuential event numbers *** , evt,oldEvt = ", evtNumber , oldEvtNumber
oldEvtNumber = evtNumber
timeStamp = lowWord & 0xFFFFFFFFFFFF
evtType = timestampData[ (evt*4) + 0] >> 28
print "bufferPos, highWord , lowWord , event-number , timestamp , evtType = %x %016x %016x %08x %012x %01x" % ( evt , highWord , lowWord, evtNumber , timeStamp , evtType)
time.sleep( loopWait)
# Fixme - at the moment infiniate loop.
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "\n\nPre,post trigger count at end of run " , preVetotriggerCount , postVetotriggerCount
firmware/scripts/test_T0.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Nasty hack - use both PyChips and uHAL ( for block read ... )
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
# Point to TLU in Pychips
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 2
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
firmwareID=board.read("FirmwareId")
print "Firmware (from PyChips) = " , hex(firmwareID)
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
clockStatus = board.read("LogicClocksCSR")
print "Clock status = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
board.write("InternalTriggerIntervalW",0)
print "Enabling DUT 0 and 1"
board.write("DUTMaskW",3)
DUTMask = board.read("DUTMaskR")
print "DUTMaskR = " , DUTMask
print "Ignore veto on DUT 0 and 1"
board.write("IgnoreDUTBusyW",3)
IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
print "IgnoreDUTBusyR = " , IgnoreDUTBusy
print "Turning off software trigger veto"
board.write("TriggerVetoW",0)
print "Reseting FIFO"
board.write("EventFifoCSR",0x2)
eventFifoFillLevel = board.read("EventFifoFillLevel")
print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
print "Enabling data recording"
board.write("Enable_Record_Data",1)
#print "Enabling handshake: No-handshake"
#board.write("HandshakeTypeW",1)
#TriggerInterval = 400000
TriggerInterval = 0
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval
print "Setting TPix_maskexternal to ignore external shutter and T0"
board.write("TPix_maskexternal",0x0003)
numLoops = 500000
oldEvtNumber = 0
for iLoop in range(0,numLoops):
board.write("TPix_T0", 0x0001)
# time.sleep( 1.0)
firmware/scripts/test_aida_tlu_data_readout.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
def mean(TS):
val=0
for i in range(1,len(TS)):
val+=TS[i]-TS[i-1]
return val/(len(TS)-1)
# Point to TLU
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 2
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
resetSerdes = 0
# set DACs to -200mV
print "Setting all threshold DAC to -200mV "
boardi2c.set_threshold_voltage(7, -0.2)
clockStatus = board.read("LogicClocksCSR")
print "Clock status = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
if resetSerdes:
board.write("SerdesRstW", 0x00000003 )
inputStatus = board.read("SerdesRstR")
print "Input status during reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000004 )
inputStatus = board.read("SerdesRstR")
print "Input status during calibration = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after calibration = " , hex(inputStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
board.write("InternalTriggerIntervalW",0)
print "Enabling DUT 0"
board.write("DUTMaskW",1)
DUTMask = board.read("DUTMaskR")
print "DUTMaskR = " , DUTMask
print "Ignore veto on DUT 1"
board.write("IgnoreDUTBusyW",2)
IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
print "IgnoreDUTBusyR = " , IgnoreDUTBusy
print "Turning off software trigger veto"
board.write("TriggerVetoW",0)
print "Reseting FIFO"
board.write("EventFifoCSR",0x2)
eventFifoFillLevel = board.read("EventFifoFillLevel")
print "FIFO fill level after resetting FIFO = " , eventFifoFillLevel
print "Enabling data recording"
board.write("Enable_Record_Data",1)
#print "Enabling handshake: No-handshake"
#board.write("HandshakeTypeW",1)
TriggerInterval = 400000
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval
numLoops = 500000
for iLoop in range(0,numLoops):
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
timestampHigh = board.read("CurrentTimestampHR")
timestampLow = board.read("CurrentTimestampLR")
print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
eventFifoFillLevel = board.read("EventFifoFillLevel")
print "FIFO fill level = " , eventFifoFillLevel
timestampData = board.blockRead("EventFifoData", eventFifoFillLevel)
time.sleep( 1.0)
firmware/scripts/test_aida_tlu_data_readout.sh deleted 100755 → 0
View file @ 6f62ad1c
#!/bin/bash
export PYTHONPATH=../PyChips_1_5_0_pre2A/src
export LD_LIBRARY_PATH=/opt/cactus/lib:$LD_LIBRARY_PATH
export PATH=/opt/cactus/bin:$PATH
python test_aida_tlu_data_readout.py
firmware/scripts/test_aida_tlu_internal_triggers.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
def mean(TS):
val=0
for i in range(1,len(TS)):
val+=TS[i]-TS[i-1]
return val/(len(TS)-1)
def pulseT0(board):
# set T0 bit to 1
PulseBits = board.read("ConfBits")
# print "ConfBits before pulseT0: ", hex(PulseBits)
PulseBits = PulseBits | 0x2
# board.write("ConfBits", PulseBits)
# print "ConfBits after pulseT0: ", hex(PulseBits)
# reset T0 bit
PulseBits = board.read("ConfBits")
PulseBits = PulseBits & 0xfffffffd
board.write("ConfBits", PulseBits)
PulseBits = board.read("ConfBits")
# print "ConfBits after reseting pulseT0: ", hex(PulseBits)
# Point to TPix3 fanout
fanoutAddrTab = AddressTable("./tpix3_fanout_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
fanoutBoard = ChipsBusUdp(fanoutAddrTab,"192.168.200.16",50001)
# set T0 width
T0width = 0x10
fanoutBoard.write("T0syncLength", T0width)
T0width = fanoutBoard.read("T0syncLength")
print "T0width = ", T0width
# POint to TLU
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 2
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
resetSerdes = 0
# set DACs to -200mV
print "Setting all threshold DAC to -200mV "
boardi2c.set_threshold_voltage(7, -0.2)
clockStatus = board.read("LogicClocksCSR")
print "Clock status = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
if resetSerdes:
board.write("SerdesRstW", 0x00000003 )
inputStatus = board.read("SerdesRstR")
print "Input status during reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after reset = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000004 )
inputStatus = board.read("SerdesRstR")
print "Input status during calibration = " , hex(inputStatus)
board.write("SerdesRstW", 0x00000000 )
inputStatus = board.read("SerdesRstR")
print "Input status after calibration = " , hex(inputStatus)
inputStatus = board.read("SerdesRstR")
print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
board.write("InternalTriggerIntervalW",0)
print "Enabling DUT 0"
board.write("DUTMaskW",1)
DUTMask = board.read("DUTMaskR")
print "DUTMaskR = " , DUTMask
print "Ignore veto on DUT 1"
board.write("IgnoreDUTBusyW",2)
IgnoreDUTBusy = board.read("IgnoreDUTBusyR")
print "IgnoreDUTBusyR = " , IgnoreDUTBusy
print "Turning off software trigger veto"
board.write("TriggerVetoW",0)
print "Reseting FIFO"
board.write("EventFifoCSR",0x2)
print "Disabling data recording"
board.write("Enable_Record_Data",0)
#print "Enabling handshake: No-handshake"
#board.write("HandshakeTypeW",1)
TriggerInterval = 160
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval
numLoops = 500000
for iLoop in range(0,numLoops):
# print "\n\nBefore reset"
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
timestampHigh = board.read("CurrentTimestampHR")
timestampLow = board.read("CurrentTimestampLR")
print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
# print "\nresetting timestamp\n"
# pulseT0(fanoutBoard)
# preVetotriggerCount = board.read("PreVetoTriggersR")
# postVetotriggerCount = board.read("PostVetoTriggersR")
# print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
# timestampHigh = board.read("CurrentTimestampHR")
# timestampLow = board.read("CurrentTimestampLR")
# print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
time.sleep( 1.0)
firmware/scripts/test_aida_tlu_internal_triggers_eudet_v2.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
#executeI2C = True
executeI2C = False
if executeI2C:
boardi2c = FmcTluI2c(board)
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
boardi2c.set_threshold_voltage(7, -0.2)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Disable data recording"
board.write("Enable_Record_Data",0)
Enable_Record_Data = board.read("Enable_Record_Data")
print "Event recording flags read back as = ",Enable_Record_Data
print "Enabling all DUTs "
board.write("DUTMaskW",7)
DUTMask = board.read("DUTMaskR")
print "DUT mask read back as " , DUTMask
print "Disable Trigger veto by DUT Busy"
board.write("IgnoreDUTBusyW", 7)
IgnoreDUTBusyW = board.read("IgnoreDUTBusyR")
print "DUT ignore BUSY veto read back as " , IgnoreDUTBusyW
print "Disable Trigger veto by DUT Shutter"
board.write("IgnoreShutterVetoW", 1)
IgnoreShutterVetoW = board.read("IgnoreShutterVetoR")
print "DUT ignore shutter veto read back as " , IgnoreShutterVetoW
print "Set DUT into EUDET mode"
board.write("DUTInterfaceModeW", 0x00)
DUTInterfaceModeR = board.read("DUTInterfaceModeR")
print "DUT mode read back as " , DUTInterfaceModeR
print "Set DUT mode modifier to zero ( don't allow DUT_CLK to veto ) "
board.write("DUTInterfaceModeModifierW", 0x00)
DUTInterfaceModeModifierR = board.read("DUTInterfaceModeModifierR")
print "DUT mode modifier read back as " , DUTInterfaceModeModifierR
print "Set Pulse stretch"
board.write("PulseStretchW", 0x00)
PulseStretchR = board.read("PulseStretchR")
print "DUT mode modifier read back as " , PulseStretchR
print "Set Pulse delay"
board.write("PulseDelayW", 0x00)
PulseDelayR = board.read("PulseDelayR")
print "DUT mode modifier read back as " , PulseDelayR
print "Turn off trigger veto"
board.write("TriggerVetoW",0)
TriggerVeto = board.read("TriggerVetoR")
print "Trigger veto read back as " , TriggerVeto
ExternalTriggerVeto = board.read("ExternalTriggerVetoR")
print "External veto = ", ExternalTriggerVeto
TriggerInterval = 0xABC
#TriggerInterval = 0x0000
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval , "(should be 2 less than written)"
LogicClocksCSR = board.read("LogicClocksCSR")
print "Clocks status = " , hex(LogicClocksCSR)
numLoops = 3
for iLoop in range(0,numLoops):
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
timestampHigh = board.read("CurrentTimestampHR")
timestampLow = board.read("CurrentTimestampLR")
print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
time.sleep( 1.0 )
firmware/scripts/test_aida_tlu_internal_triggers_v2.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
executeI2C = True
#executeI2C = False
if executeI2C:
boardi2c = FmcTluI2c(board)
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
boardi2c.set_threshold_voltage(7, -0.2)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
print "Disable data recording"
board.write("Enable_Record_Data",0)
Enable_Record_Data = board.read("Enable_Record_Data")
print "Event recording flags read back as = ",Enable_Record_Data
print "Enabling all DUTs "
board.write("DUTMaskW",7)
DUTMask = board.read("DUTMaskR")
print "DUT mask read back as " , DUTMask
print "Disable Trigger veto by DUT Busy"
board.write("IgnoreDUTBusyW", 7)
IgnoreDUTBusyW = board.read("IgnoreDUTBusyR")
print "DUT ignore BUSY veto read back as " , IgnoreDUTBusyW
print "Disable Trigger veto by DUT Shutter"
board.write("IgnoreShutterVetoW", 1)
IgnoreShutterVetoW = board.read("IgnoreShutterVetoR")
print "DUT ignore shutter veto read back as " , IgnoreShutterVetoW
print "Set DUT into AIDA mode"
board.write("DUTInterfaceModeW", 0xFF)
DUTInterfaceModeR = board.read("DUTInterfaceModeR")
print "DUT mode read back as " , DUTInterfaceModeR
print "Set DUT mode modifier"
board.write("DUTInterfaceModeModifierW", 0xFF)
DUTInterfaceModeModifierR = board.read("DUTInterfaceModeModifierR")
print "DUT mode modifier read back as " , DUTInterfaceModeModifierR
print "Set Pulse stretch"
board.write("PulseStretchW", 0x00)
PulseStretchR = board.read("PulseStretchR")
print "DUT mode modifier read back as " , PulseStretchR
print "Set Pulse delay"
board.write("PulseDelayW", 0x00)
PulseDelayR = board.read("PulseDelayR")
print "DUT mode modifier read back as " , PulseDelayR
print "Turn off trigger veto"
board.write("TriggerVetoW",0)
TriggerVeto = board.read("TriggerVetoR")
print "Trigger veto read back as " , TriggerVeto
ExternalTriggerVeto = board.read("ExternalTriggerVetoR")
print "External veto = ", ExternalTriggerVeto
TriggerInterval = 0xABC
#TriggerInterval = 0x0000
print "Setting internal trigger interval to " , TriggerInterval
board.write("InternalTriggerIntervalW",TriggerInterval) #0->Internal pulse generator disabled. Any other value will generate pulses with a frequency of n*6.25ns
trigInterval = board.read("InternalTriggerIntervalR")
print "Trigger interval read back as ", trigInterval , "(should be 2 less than written)"
LogicClocksCSR = board.read("LogicClocksCSR")
print "Clocks status = " , hex(LogicClocksCSR)
numLoops = 3
for iLoop in range(0,numLoops):
preVetotriggerCount = board.read("PreVetoTriggersR")
postVetotriggerCount = board.read("PostVetoTriggersR")
print "pre , post veto triggers = " , preVetotriggerCount , postVetotriggerCount
timestampHigh = board.read("CurrentTimestampHR")
timestampLow = board.read("CurrentTimestampLR")
print "Current timestamp High,Low (hex) = " , hex(timestampHigh) , hex(timestampLow)
time.sleep( 1.0 )
firmware/scripts/test_aida_tlu_trig_counter.py deleted 100644 → 0
View file @ 6f62ad1c
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
boardIpAddr = "192.168.200.16"
boardPortNum = 50001
addrTable = AddressTable("./aida_mini_tlu_addr_map.txt")
board = ChipsBusUdp(addrTable, boardIpAddr, boardPortNum)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
boardFirmware = board.read("FirmwareId")
print "Firmware version = " , hex(boardFirmware)
print "Scanning I2C bus:"
scanResults = boardi2c.i2c_scan()
print scanResults
boardId = boardi2c.get_serial_number()
print "FMC-TLU serial number = " , boardId
resetClocks = 0
resetSerdes = 0
# set DACs to -200mV
print "Setting all threshold DAC to -200mV "
boardi2c.set_threshold_voltage(7, -0.200)
clockStatus = board.read("LogicClocksCSR")
print "Clock status = " , hex(clockStatus)
if resetClocks:
print "Resetting clocks"
board.write("LogicRst", 1 )
clockStatus = board.read("LogicClocksCSR")
print "Clock status after reset = " , hex(clockStatus)
#print "Setting PLL input to ext. clk"
#board.write("LogicRst", 0 )
#clockStatus = board.read("LogicClocksCSR")
#print "Clock status = " , hex(clockStatus)
# Not all version of firmware have a serdes reset addres...
#inputStatus = board.read("SerdesRst")
#print "Input status = " , hex(inputStatus)
if resetSerdes :
board.write("SerdesRst", 0x00000003 )
inputStatus = board.read("SerdesRst")
print "Input status during reset = " , hex(inputStatus)
board.write("SerdesRst", 0x00000000 )
inputStatus = board.read("SerdesRst")
print "Input status after reset = " , hex(inputStatus)
board.write("SerdesRst", 0x00000004 )
inputStatus = board.read("SerdesRst")
print "Input status during calibration = " , hex(inputStatus)
board.write("SerdesRst", 0x00000000 )
inputStatus = board.read("SerdesRst")
print "Input status after calibration = " , hex(inputStatus)
# Look at status of input IODELAYs
numLoops = 5
for iLoop in range(0,numLoops):
#inputStatus = board.read("SerdesRst")
#print "Input status = " , hex(inputStatus)
count0 = board.read("ThrCount0R")
print " Count 0 = " , count0
count1 = board.read("ThrCount1R")
print " Count 1 = " , count1
count2 = board.read("ThrCount2R")
print " Count 2 = " , count2
count3 = board.read("ThrCount3R")
print " Count 3 = " , count3
time.sleep(1.0)
firmware/scripts/test_triggerPattern_load.py deleted 100644 → 0
View file @ 6f62ad1c
#
# Script to exercise AIDA mini-TLU
#
# David Cussans, December 2012
#
# Hacked to only test internal triggers
from PyChipsUser import *
from FmcTluI2c import *
import sys
import time
def mean(TS):
val=0
for i in range(1,len(TS)):
val+=TS[i]-TS[i-1]
return val/(len(TS)-1)
bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
# Assume DIP-switch controlled address. Switches at 1
board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)
# Check the bus for I2C devices
boardi2c = FmcTluI2c(board)
firmwareID=board.read("FirmwareId")
print "Firmware = " , hex(firmwareID)
board.write("TriggerVetoRW",0)
veto = board.read("TriggerVetoRW")
print "Trigger Veto = " , hex(veto)
board.write("TriggerPatternRW",0x1234ABCD)
triggerPattern = board.read("TriggerPatternRW")
print "Trigger Pattern = " , hex(triggerPattern)
board.write("TriggerPatternRW",0xFFFEFFFE)
triggerPattern = board.read("TriggerPatternRW")
print "Trigger Pattern = " , hex(triggerPattern)
firmware/scripts/tpix3_fanout_addr_map.txt deleted 100644 → 0
View file @ 6f62ad1c
*RegName RegAddr RegMask R W
*-------------------------------------------------------------
FirmwareId 0x00000000 0xffffffff 1 0
* DUT interfaces base = 0x010
ConfBits 0x00000011 0xffffffff 1 1
T0syncLength 0x00000012 0xffffffff 1 1
BusyMask 0x00000013 0xffffffff 1 1
ConfBitsR 0x00000019 0xffffffff 1 1
BusyMaskR 0x0000001b 0xffffffff 1 1
firmware/ucf/SP601_fmc_connections.ucf deleted 100644 → 0
View file @ 6f62ad1c
NET "FMC_CLK0_M2C_N" LOC = "A10"; ## H5 on J1
NET "FMC_CLK0_M2C_P" LOC = "C10"; ## H4 on J1
NET "FMC_CLK1_M2C_N" LOC = "V9"; ## G3 on J1
NET "FMC_CLK1_M2C_P" LOC = "T9"; ## G2 on J1
NET "FMC_LA00_CC_N" LOC = "C9"; ## G7 on J1
NET "FMC_LA00_CC_P" LOC = "D9"; ## G6 on J1
NET "FMC_LA01_CC_N" LOC = "C11"; ## D9 on J1
NET "FMC_LA01_CC_P" LOC = "D11"; ## D8 on J1
NET "FMC_LA02_N" LOC = "A15"; ## H8 on J1
NET "FMC_LA02_P" LOC = "C15"; ## H7 on J1
NET "FMC_LA03_N" LOC = "A13"; ## G10 on J1
NET "FMC_LA03_P" LOC = "C13"; ## G9 on J1
NET "FMC_LA04_N" LOC = "A16"; ## H11 on J1
NET "FMC_LA04_P" LOC = "B16"; ## H10 on J1
NET "FMC_LA05_N" LOC = "A14"; ## D12 on J1
NET "FMC_LA05_P" LOC = "B14"; ## D11 on J1
NET "FMC_LA06_N" LOC = "C12"; ## C11 on J1
NET "FMC_LA06_P" LOC = "D12"; ## C10 on J1
NET "FMC_LA07_N" LOC = "E8"; ## H14 on J1
NET "FMC_LA07_P" LOC = "E7"; ## H13 on J1
NET "FMC_LA08_N" LOC = "E11"; ## G13 on J1
NET "FMC_LA08_P" LOC = "F11"; ## G12 on J1
NET "FMC_LA09_N" LOC = "F10"; ## D15 on J1
NET "FMC_LA09_P" LOC = "G11"; ## D14 on J1
NET "FMC_LA10_N" LOC = "C8"; ## C15 on J1
NET "FMC_LA10_P" LOC = "D8"; ## C14 on J1
NET "FMC_LA11_N" LOC = "A12"; ## H17 on J1
NET "FMC_LA11_P" LOC = "B12"; ## H16 on J1
NET "FMC_LA12_N" LOC = "C6"; ## G16 on J1
NET "FMC_LA12_P" LOC = "D6"; ## G15 on J1
NET "FMC_LA13_N" LOC = "A11"; ## D18 on J1
NET "FMC_LA13_P" LOC = "B11"; ## D17 on J1
NET "FMC_LA14_N" LOC = "A2"; ## C19 on J1
NET "FMC_LA14_P" LOC = "B2"; ## C18 on J1
NET "FMC_LA15_N" LOC = "F9"; ## H20 on J1
NET "FMC_LA15_P" LOC = "G9"; ## H19 on J1
NET "FMC_LA16_N" LOC = "A7"; ## G19 on J1
NET "FMC_LA16_P" LOC = "C7"; ## G18 on J1
NET "FMC_LA17_CC_N" LOC = "T8"; ## D21 on J1
NET "FMC_LA17_CC_P" LOC = "R8"; ## D20 on J1
NET "FMC_LA18_CC_N" LOC = "T10"; ## C23 on J1
NET "FMC_LA18_CC_P" LOC = "R10"; ## C22 on J1
NET "FMC_LA19_N" LOC = "P7"; ## H23 on J1
NET "FMC_LA19_P" LOC = "N6"; ## H22 on J1
NET "FMC_LA20_N" LOC = "P8"; ## G22 on J1
NET "FMC_LA20_P" LOC = "N7"; ## G21 on J1
NET "FMC_LA21_N" LOC = "V4"; ## H26 on J1
NET "FMC_LA21_P" LOC = "T4"; ## H25 on J1
NET "FMC_LA22_N" LOC = "T7"; ## G25 on J1
NET "FMC_LA22_P" LOC = "R7"; ## G24 on J1
NET "FMC_LA23_N" LOC = "P6"; ## D24 on J1
NET "FMC_LA23_P" LOC = "N5"; ## D23 on J1
NET "FMC_LA24_N" LOC = "V8"; ## H29 on J1
NET "FMC_LA24_P" LOC = "U8"; ## H28 on J1
NET "FMC_LA25_N" LOC = "N11"; ## G28 on J1
NET "FMC_LA25_P" LOC = "M11"; ## G27 on J1
NET "FMC_LA26_N" LOC = "V7"; ## D27 on J1
NET "FMC_LA26_P" LOC = "U7"; ## D26 on J1
NET "FMC_LA27_N" LOC = "T11"; ## C27 on J1
NET "FMC_LA27_P" LOC = "R11"; ## C26 on J1
NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
NET "FMC_LA32_N" LOC = "V15"; ## H38 on J1
NET "FMC_LA32_P" LOC = "U15"; ## H37 on J1
NET "FMC_LA33_N" LOC = "N9"; ## G37 on J1
NET "FMC_LA33_P" LOC = "M10"; ## G36 on J1
firmware/ucf/SP601_fmc_connections_v2.ucf deleted 100644 → 0
View file @ 6f62ad1c
NET "FMC_CLK0_M2C_N" LOC = "A10"; ## H5 on J1
NET "FMC_CLK0_M2C_P" LOC = "C10"; ## H4 on J1
NET "FMC_CLK1_M2C_N" LOC = "V9"; ## G3 on J1
NET "FMC_CLK1_M2C_P" LOC = "T9"; ## G2 on J1
NET "FMC_LA00_CC_N" LOC = "C9"; ## G7 on J1
NET "FMC_LA00_CC_P" LOC = "D9"; ## G6 on J1
NET "FMC_LA01_CC_N" LOC = "C11"; ## D9 on J1
NET "FMC_LA01_CC_P" LOC = "D11"; ## D8 on J1
NET "FMC_LA02_N" LOC = "A15"; ## H8 on J1
NET "FMC_LA02_P" LOC = "C15"; ## H7 on J1
NET "FMC_LA03_N" LOC = "A13"; ## G10 on J1
NET "FMC_LA03_P" LOC = "C13"; ## G9 on J1
NET "FMC_LA04_N" LOC = "A16"; ## H11 on J1
NET "FMC_LA04_P" LOC = "B16"; ## H10 on J1
NET "FMC_LA05_N" LOC = "A14"; ## D12 on J1
NET "FMC_LA05_P" LOC = "B14"; ## D11 on J1
NET "FMC_LA06_N" LOC = "C12"; ## C11 on J1
NET "FMC_LA06_P" LOC = "D12"; ## C10 on J1
NET "FMC_LA07_N" LOC = "E8"; ## H14 on J1
NET "FMC_LA07_P" LOC = "E7"; ## H13 on J1
NET "FMC_LA08_N" LOC = "E11"; ## G13 on J1
NET "FMC_LA08_P" LOC = "F11"; ## G12 on J1
NET "FMC_LA09_N" LOC = "F10"; ## D15 on J1
NET "FMC_LA09_P" LOC = "G11"; ## D14 on J1
NET "FMC_LA10_N" LOC = "C8"; ## C15 on J1
NET "FMC_LA10_P" LOC = "D8"; ## C14 on J1
NET "FMC_LA11_N" LOC = "A12"; ## H17 on J1
NET "FMC_LA11_P" LOC = "B12"; ## H16 on J1
NET "FMC_LA12_N" LOC = "C6"; ## G16 on J1
NET "FMC_LA12_P" LOC = "D6"; ## G15 on J1
NET "FMC_LA13_N" LOC = "A11"; ## D18 on J1
NET "FMC_LA13_P" LOC = "B11"; ## D17 on J1
NET "FMC_LA14_N" LOC = "A2"; ## C19 on J1
NET "FMC_LA14_P" LOC = "B2"; ## C18 on J1
NET "FMC_LA15_N" LOC = "F9"; ## H20 on J1
NET "FMC_LA15_P" LOC = "G9"; ## H19 on J1
NET "FMC_LA16_N" LOC = "A7"; ## G19 on J1
NET "FMC_LA16_P" LOC = "C7"; ## G18 on J1
NET "FMC_LA17_CC_N" LOC = "T8"; ## D21 on J1
NET "FMC_LA17_CC_P" LOC = "R8"; ## D20 on J1
NET "FMC_LA18_CC_N" LOC = "T10"; ## C23 on J1
NET "FMC_LA18_CC_P" LOC = "R10"; ## C22 on J1
NET "FMC_LA19_N" LOC = "P7"; ## H23 on J1
NET "FMC_LA19_P" LOC = "N6"; ## H22 on J1
NET "FMC_LA20_N" LOC = "P8"; ## G22 on J1
NET "FMC_LA20_P" LOC = "N7"; ## G21 on J1
NET "FMC_LA21_N" LOC = "V4"; ## H26 on J1
NET "FMC_LA21_P" LOC = "T4"; ## H25 on J1
NET "FMC_LA22_N" LOC = "T7"; ## G25 on J1
NET "FMC_LA22_P" LOC = "R7"; ## G24 on J1
NET "FMC_LA23_N" LOC = "P6"; ## D24 on J1
NET "FMC_LA23_P" LOC = "N5"; ## D23 on J1
NET "FMC_LA24_N" LOC = "V8"; ## H29 on J1
NET "FMC_LA24_P" LOC = "U8"; ## H28 on J1
NET "FMC_LA25_N" LOC = "N11"; ## G28 on J1
NET "FMC_LA25_P" LOC = "M11"; ## G27 on J1
NET "FMC_LA26_N" LOC = "V7"; ## D27 on J1
NET "FMC_LA26_P" LOC = "U7"; ## D26 on J1
NET "FMC_LA27_N" LOC = "T11"; ## C27 on J1
NET "FMC_LA27_P" LOC = "R11"; ## C26 on J1
NET "FMC_LA28_N" LOC = "V11"; ## H32 on J1
NET "FMC_LA28_P" LOC = "U11"; ## H31 on J1
NET "FMC_LA29_N" LOC = "N8"; ## G31 on J1
NET "FMC_LA29_P" LOC = "M8"; ## G30 on J1
NET "FMC_LA30_N" LOC = "V12"; ## H35 on J1
NET "FMC_LA30_P" LOC = "T12"; ## H34 on J1
NET "FMC_LA31_N" LOC = "V6"; ## G34 on J1
NET "FMC_LA31_P" LOC = "T6"; ## G33 on J1
NET "FMC_LA32_N" LOC = "V15"; ## H38 on J1
NET "FMC_LA32_P" LOC = "U15"; ## H37 on J1
NET "FMC_LA33_N" LOC = "N9"; ## G37 on J1
NET "FMC_LA33_P" LOC = "M10"; ## G36 on J1
NET "FMC_PRSNT_M2C_L" LOC = "U13"; ## H2 on J1
NET "FMC_PWR_GOOD_FLASH_RST_B" LOC = "B3"; ## D1 on J1, 16 on U10
NET "FPGA_CCLK" LOC = "R15"; ## 16 on U17, 7 on J12
NET "FPGA_D0_DIN_MISO_MISO1" LOC = "R13"; ## 8 on U17 (thru series R187 100 ohm), 33 on U10, 6 on J12
NET "FPGA_D1_MISO2" LOC = "T14"; ## 9 on U17 (thru series R186 100 ohm), 35 on U10, 3 on J12
NET "FPGA_D2_MISO3" LOC = "V14"; ## 1 on U17, 38 on U10, 2 on J12
NET "FPGA_MOSI_CSI_B_MISO0" LOC = "T13"; ## 15 on U17, 5 on J12
NET "FPGA_SUSPEND" LOC = "R16"; ## 2 on J14
NET "FPGA_TCK_BUF" LOC = "A17"; ## 14 on U21, D29 on J1
NET "FPGA_TDO" LOC = "D16"; ## 1 on J4, D30 on J1
NET "FPGA_TMS_BUF" LOC = "B18"; ## 16 on U21, D31 on J1
NET "GPIO_HDR0" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
NET "GPIO_HDR1" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
NET "GPIO_HDR2" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
NET "GPIO_HDR3" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
NET "GPIO_HDR4" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
NET "GPIO_HDR5" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
NET "GPIO_HDR6" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
NET "GPIO_HDR7" LOC = "P12"; ## 8 on J13 (thru series R96 200 ohm)
NET "IIC_SCL_MAIN" LOC = "P11"; ## 6 on U7 (thru series R203 0 ohm), C30 on J1, 2 on J16
NET "IIC_SDA_MAIN" LOC = "N10"; ## 5 on U7 (thru series R204 0 ohm), C31 on J1, 1 on J16
NET "SPI_CS_B" LOC = "V3"; ## 1 on J15, 4 on J12
firmware/ucf/fmc_pins.ucf deleted 100644 → 0
View file @ 6f62ad1c
NET "BUSY_P<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
NET "BUSY_N<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
NET "TRIG_P<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
NET "TRIG_N<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
NET "BEAM_TRIGGER_CFD_P<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
NET "BEAM_TRIGGER_CFD_N<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
NET "BEAM_TRIGGER_CFD_P<2>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
NET "BEAM_TRIGGER_CFD_N<2>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
NET "BEAM_TRIGGER_CFD_P<3>" LOC = "R11"; ## "FMC_LA27_P" , C26 on FMC
NET "BEAM_TRIGGER_CFD_N<3>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
NET "SCL" LOC = "P11"; ## C30 on FMC
NET "SDA" LOC = "N10"; ## C31 on FMC
NET "TRIG_P<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
NET "TRIG_N<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
NET "BEAM_TRIGGER_P<1>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
NET "BEAM_TRIGGER_N<1>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
NET "BEAM_TRIGGER_P<2>" LOC = "N5"; ## "FMC_LA23_P" , D23 on FMC
NET "BEAM_TRIGGER_N<2>" LOC = "P6"; ## "FMC_LA23_N" , D24 on FMC
NET "BEAM_TRIGGER_P<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
NET "BEAM_TRIGGER_N<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "CONT_P<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC
NET "CONT_N<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC
NET "BEAM_TRIGGER_P<3>" LOC = "M8"; ## "FMC_LA29_P" , G30 on FMC
NET "BEAM_TRIGGER_N<3>" LOC = "N8"; ## "FMC_LA29_N" , G31 on FMC
NET "DUT_CLK_P<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC
NET "DUT_CLK_N<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC
NET "CONT_P<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC
NET "CONT_N<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC
NET "BEAM_TRIGGER_CFD_P<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
NET "BEAM_TRIGGER_CFD_N<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
NET "CLK_P<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
NET "CLK_N<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC
NET "BUSY_P<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
NET "BUSY_N<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
NET "CLK_P<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC
NET "CLK_N<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
NET "CONT_P<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC
NET "CONT_N<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC
NET "BUSY_P<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
NET "BUSY_N<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
NET "TRIG_P<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
NET "TRIG_N<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
NET "FRONT_PANEL_CLK_P" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC
NET "FRONT_PANEL_CLK_N" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC
NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
firmware/ucf/sp601_FMC_mTLU.ucf deleted 100644 → 0
View file @ 6f62ad1c
NET sysclk_p_i LOC = K15 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K16 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET I6/s_clk_is_xtal TIG;
NET leds_o<0> LOC=E13 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=C14 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=C4 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=A4 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=D14;
NET dip_switch_i<1> LOC=E12;
NET dip_switch_i<2> LOC=F12;
NET dip_switch_i<3> LOC=V13;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=A9 | IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=F8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=G8 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=A6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=B6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=E6 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=F7 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=A5 | IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=C5 | IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=B8 | IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=A8 | IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=L16 | IOSTANDARD=LVCMOS25 | TNM_NET= "gmii_rx_clk_i";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=M14 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=U18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=U17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=T18 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=T17 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=N16 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=N15 | IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=P18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=N18 | IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=P17 | IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=L13 | IOSTANDARD=LVCMOS25;
# Main I2C bus
NET "I2C_SCL_B" LOC = "P11"; ## C30 on FMC
NET "I2C_SDA_B" LOC = "N10"; ## C31 on FMC
#
# I/O to devices under test
NET "BUSY_P_I<0>" LOC = "D12"; ## "FMC_LA06_P" , C10 on FMC
NET "BUSY_N_I<0>" LOC = "C12"; ## "FMC_LA06_N" , C11 on FMC
NET "BUSY_P_I<1>" LOC = "U11"; ## "FMC_LA28_P" , H31 on FMC
NET "BUSY_N_I<1>" LOC = "V11"; ## "FMC_LA28_N" , H32 on FMC
NET "BUSY_P_I<2>" LOC = "E7"; ## "FMC_LA07_P" , H13 on FMC
NET "BUSY_N_I<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
NET "TRIGGERS_P_O<0>" LOC = "D8"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "C8"; ## "FMC_LA10_N" , C15 on FMC
NET "TRIGGERS_P_O<1>" LOC = "U15"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "V15"; ## "FMC_LA32_N" , H38 on FMC
NET "TRIGGERS_P_O<2>" LOC = "G11"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F10"; ## "FMC_LA09_N" , D15 on FMC
# Remove for now.
#NET "SHUTTERS_P_O<0>" LOC = "N7"; ## "FMC_LA20_P" , G21 on FMC
##NET "SHUTTERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "R10"; ## "FMC_LA18_CC_P" , C22 on FMC
##NET "SHUTTERS_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "N6"; ## "FMC_LA19_P" , H22 on FMC
##NET "SHUTTERS_N_O<2>" LOC = "P6"; ## "FMC_LA19_N" , H23 on FMC
NET "DUT_CLK_P_I<0>" LOC = "T6"; ## "FMC_LA31_P" , G33 on FMC , DUT_CLK_P_I<0>
NET "DUT_CLK_N_I<0>" LOC = "V6"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N_I<0>
NET "DUT_CLK_P_I<1>" LOC = "T4"; ## "FMC_LA21_P" , H25 on FMC , DUT_CLK_P_I<0>
#NET "DUT_CLK_P_I<1>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC , DUT_CLK_N_I<0>
NET "DUT_CLK_P_I<2>" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC , DUT_CLK_P_I<0>
#NET "DUT_CLK_P_I<2>" LOC = "A16"; ## "FMC_LA04_N" , H11 on FMC , DUT_CLK_N_I<0>
NET "RESET_OR_CLK_P_O<0>" LOC = "M10"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
#NET "RESET_OR_CLK_N_O<0>" LOC = "N9"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
NET "RESET_OR_CLK_P_O<1>" LOC = "U8"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
NET "RESET_OR_CLK_N_O<1>" LOC = "V8"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
NET "RESET_OR_CLK_P_O<2>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
NET "RESET_OR_CLK_N_O<2>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
NET "CFD_DISCR_P_I<0>" LOC = "D9"; ## "FMC_LA00_CC_P" , G6 on FMC
NET "CFD_DISCR_N_I<0>" LOC = "C9"; ## "FMC_LA00_CC_N" , G7 on FMC
NET "CFD_DISCR_P_I<1>" LOC = "B2"; ## "FMC_LA14_P" , C18 on FMC
NET "CFD_DISCR_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
NET "CFD_DISCR_P_I<2>" LOC = "B14"; ## "FMC_LA05_P" , D11 on FMC
NET "CFD_DISCR_N_I<2>" LOC = "A14"; ## "FMC_LA05_N" , D12 on FMC
NET "CFD_DISCR_P_I<3>" LOC = "B11"; ## "FMC_LA13_P" , D17 on FMC
NET "CFD_DISCR_N_I<3>" LOC = "A11"; ## "FMC_LA13_N" , D18 on FMC
# Threshold comparator outputs
NET "THRESHOLD_DISCR_P_I<0>" LOC = "D11"; ## "FMC_LA01_CC_P" , D8 on FMC
NET "THRESHOLD_DISCR_N_I<0>" LOC = "C11"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "C13"; ## "FMC_LA03_P" , G9 on FMC
NET "THRESHOLD_DISCR_N_I<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D6"; ## "FMC_LA12_P" , G15 on FMC
NET "THRESHOLD_DISCR_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "C7"; ## "FMC_LA16_P" , G18 on FMC
NET "THRESHOLD_DISCR_N_I<3>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
#NET "SPARE_P<2>" LOC = "R8"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "T8"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "T12"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "V12"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "C10"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "A10"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "C15"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
# GPIO pins for debugging.
NET "GPIO_HDR<0>" LOC = "N17"; ## 1 on J13 (thru series R100 200 ohm)
NET "GPIO_HDR<1>" LOC = "M18"; ## 3 on J13 (thru series R102 200 ohm)
NET "GPIO_HDR<2>" LOC = "A3"; ## 5 on J13 (thru series R101 200 ohm)
NET "GPIO_HDR<3>" LOC = "L15"; ## 7 on J13 (thru series R103 200 ohm)
NET "GPIO_HDR<4>" LOC = "F15"; ## 2 on J13 (thru series R99 200 ohm)
NET "GPIO_HDR<5>" LOC = "B4"; ## 4 on J13 (thru series R98 200 ohm)
NET "GPIO_HDR<6>" LOC = "F13"; ## 6 on J13 (thru series R97 200 ohm)
NET "GPIO_HDR<7>" LOC = "P12"; ## 8 on J13 (thru series R96 20
\ No newline at end of file
firmware/ucf/sp601_FMC_mTLU_v1a.ucf deleted 100644 → 0
View file @ 6f62ad1c
#
# UCF for version 1a of updated mini-TLU
#
NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
NET "sysclk_p_i" LOC = K15;
NET "sysclk_p_i" IOSTANDARD = LVDS_25;
NET "sysclk_p_i" DIFF_TERM = "TRUE";
NET "sysclk_n_i" LOC = K16;
NET "sysclk_n_i" IOSTANDARD = LVDS_25;
NET "sysclk_n_i" DIFF_TERM = "TRUE";
TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET "I6/s_clk_is_xtal" TIG;
NET "leds_o[0]" LOC = E13;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" LOC = C14;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" LOC = C4;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" LOC = A4;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "dip_switch_i[0]" LOC = D14;
NET "dip_switch_i[1]" LOC = E12;
NET "dip_switch_i[2]" LOC = F12;
NET "dip_switch_i[3]" LOC = V13;
# Ethernet PHY
TIMEGRP TG_gmii_tx = PADS("gmii_tx*");
TIMEGRP "TG_gmii_tx" OFFSET = OUT AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET "gmii_gtx_clk_o" LOC = A9;
NET "gmii_gtx_clk_o" IOSTANDARD = LVCMOS25;
NET "gmii_gtx_clk_o" SLEW = FAST;
NET "gmii_txd_o[0]" LOC = F8;
NET "gmii_txd_o[0]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[1]" LOC = G8;
NET "gmii_txd_o[1]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[2]" LOC = A6;
NET "gmii_txd_o[2]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[3]" LOC = B6;
NET "gmii_txd_o[3]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[4]" LOC = E6;
NET "gmii_txd_o[4]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[5]" LOC = F7;
NET "gmii_txd_o[5]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[6]" LOC = A5;
NET "gmii_txd_o[6]" IOSTANDARD = LVCMOS25;
NET "gmii_txd_o[7]" LOC = C5;
NET "gmii_txd_o[7]" IOSTANDARD = LVCMOS25;
NET "gmii_tx_en_o" LOC = B8;
NET "gmii_tx_en_o" IOSTANDARD = LVCMOS25;
NET "gmii_tx_er_o" LOC = A8;
NET "gmii_tx_er_o" IOSTANDARD = LVCMOS25;
NET "gmii_rx_clk_i" TNM_NET = "gmii_rx_clk_i";
NET "gmii_rx_clk_i" LOC = L16;
NET "gmii_rx_clk_i" IOSTANDARD = LVCMOS25;
TIMESPEC TS_GMII_RX_CLK_I = PERIOD "gmii_rx_clk_i" 125 MHz;
OFFSET = IN 2 ns VALID 3 ns BEFORE "gmii_rx_clk_i";
NET "gmii_rxd_i[0]" LOC = M14;
NET "gmii_rxd_i[0]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[1]" LOC = U18;
NET "gmii_rxd_i[1]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[2]" LOC = U17;
NET "gmii_rxd_i[2]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[3]" LOC = T18;
NET "gmii_rxd_i[3]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[4]" LOC = T17;
NET "gmii_rxd_i[4]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[5]" LOC = N16;
NET "gmii_rxd_i[5]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[6]" LOC = N15;
NET "gmii_rxd_i[6]" IOSTANDARD = LVCMOS25;
NET "gmii_rxd_i[7]" LOC = P18;
NET "gmii_rxd_i[7]" IOSTANDARD = LVCMOS25;
NET "gmii_rx_dv_i" LOC = N18;
NET "gmii_rx_dv_i" IOSTANDARD = LVCMOS25;
NET "gmii_rx_er_i" LOC = P17;
NET "gmii_rx_er_i" IOSTANDARD = LVCMOS25;
NET "phy_rstb_o" LOC = L13;
NET "phy_rstb_o" IOSTANDARD = LVCMOS25;
# Main I2C bus
## C30 on FMC
NET "i2c_scl_b" LOC = P11;
## C31 on FMC
NET "i2c_sda_b" LOC = N10;
#
# I/O to devices under test
#NET "BUSY_N_I<0>" LOC = "P7"; ## "FMC_LA19_N" , H23 on FMC
#NET "BUSY_N_I<1>" LOC = "A2"; ## "FMC_LA14_N" , C19 on FMC
#NET "BUSY_N_I<2>" LOC = "C6"; ## "FMC_LA12_N" , G16 on FMC
## "FMC_LA19_P" , H22 on FMC
NET "busy_p_i[0]" LOC = N6;
## "FMC_LA14_P" , C18 on FMC
NET "busy_p_i[1]" LOC = B2;
## "FMC_LA12_P" , G15 on FMC
NET "busy_p_i[2]" LOC = D6;
#NET "TRIGGERS_N_O<0>" LOC = "P8"; ## "FMC_LA20_N" , G22 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "A13"; ## "FMC_LA03_N" , G10 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "A7"; ## "FMC_LA16_N" , G19 on FMC
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = N7;
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[1]" LOC = C13;
## "FMC_LA16_P" , G18 on FMC
NET "triggers_p_o[2]" LOC = C7;
# Remove shutters ( also known as SPARE ) for now
#NET "SPARE_N_O<1>" LOC = "E11"; ## "FMC_LA08_N" , G13 on FMC
#NET "SPARE_N_O<2>" LOC = "A12"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P_O<1>" LOC = "F11"; ## "FMC_LA08_P" , G12 on FMC
#NET "SPARE_P_O<2>" LOC = "B12"; ## "FMC_LA11_P" , H16 on FMC
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
#NET "DUT_CLK_N_I<0>" LOC = "V4"; ## "FMC_LA21_N" , H26 on FMC
#NET "DUT_CLK_N_I<1>" LOC = "T11"; ## "FMC_LA27_N" , C27 on FMC
#NET "DUT_CLK_N_I<2>" LOC = "A15"; ## "FMC_LA02_N" , H8 on FMC
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_o[0]" LOC = T4;
## "FMC_LA27_P" , C26 on FMC
NET "dut_clk_p_o[1]" LOC = R11;
## "FMC_LA02_P" , H7 on FMC
NET "dut_clk_p_o[2]" LOC = C15;
# Labelled CONT on schematic.
#NET "RESET_OR_CLK_N_O<0>" LOC = "T7"; ## "FMC_LA22_N" , G25 on FMC
#NET "RESET_OR_CLK_N_O<1>" LOC = "T10"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "RESET_OR_CLK_N_O<2>" LOC = "E8"; ## "FMC_LA07_N" , H14 on FMC
## "FMC_LA22_P" , G24 on FMC
NET "reset_or_clk_p_o[0]" LOC = R7;
## "FMC_LA18_CC_P" , C22 on FMC
NET "reset_or_clk_p_o[1]" LOC = R10;
## "FMC_LA07_P" , H13 on FMC
NET "reset_or_clk_p_o[2]" LOC = E7;
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
## "FMC_LA32_N" , H38 on FMC
NET "cfd_discr_n_i[0]" LOC = V15;
## "FMC_LA30_N" , H35 on FMC
NET "cfd_discr_n_i[1]" LOC = V12;
## "FMC_LA28_N" , H32 on FMC
NET "cfd_discr_n_i[2]" LOC = V11;
## "FMC_LA24_N" , H29 on FMC
NET "cfd_discr_n_i[3]" LOC = V8;
## "FMC_LA32_P" , H37 on FMC
NET "cfd_discr_p_i[0]" LOC = U15;
## "FMC_LA30_P" , H34 on FMC
NET "cfd_discr_p_i[1]" LOC = T12;
## "FMC_LA28_P" , H31 on FMC
NET "cfd_discr_p_i[2]" LOC = U11;
## "FMC_LA24_P" , H28 on FMC
NET "cfd_discr_p_i[3]" LOC = U8;
# Threshold comparator outputs
## "FMC_LA33_N" , G37 on FMC
NET "threshold_discr_n_i[0]" LOC = N9;
## "FMC_LA31_N" , G34 on FMC
NET "threshold_discr_n_i[1]" LOC = V6;
## "FMC_LA29_N" , G31 on FMC
NET "threshold_discr_n_i[2]" LOC = N8;
## "FMC_LA25_N" , G28 on FMC
NET "threshold_discr_n_i[3]" LOC = N11;
## "FMC_LA33_P" , G36 on FMC
NET "threshold_discr_p_i[0]" LOC = M10;
## "FMC_LA31_P" , G33 on FMC
NET "threshold_discr_p_i[1]" LOC = T6;
## "FMC_LA29_P" , G30 on FMC
NET "threshold_discr_p_i[2]" LOC = M8;
## "FMC_LA25_P" , G27 on FMC
NET "threshold_discr_p_i[3]" LOC = M11;
############
# External clock pins
## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "extclk_p_b" LOC = C10;
## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
NET "extclk_n_b" LOC = A10;
#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
# GPIO pins for debugging.
## 1 on J13 (thru series R100 200 ohm)
NET "gpio_hdr[0]" LOC = N17;
## 3 on J13 (thru series R102 200 ohm)
NET "gpio_hdr[1]" LOC = M18;
## 5 on J13 (thru series R101 200 ohm)
NET "gpio_hdr[2]" LOC = A3;
## 7 on J13 (thru series R103 200 ohm)
NET "gpio_hdr[3]" LOC = L15;
## 2 on J13 (thru series R99 200 ohm)
NET "gpio_hdr[4]" LOC = F15;
## 4 on J13 (thru series R98 200 ohm)
NET "gpio_hdr[5]" LOC = B4;
## 6 on J13 (thru series R97 200 ohm)
NET "gpio_hdr[6]" LOC = F13;
## 8 on J13 (thru series R96 20
NET "gpio_hdr[7]" LOC = P12;
firmware/ucf/sp605_FMC_mTLU.ucf deleted 100644 → 0
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NET sysclk_p_i LOC = K21 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE | TNM_NET = tnm_sysclk;
NET sysclk_n_i LOC = K22 | IOSTANDARD = LVDS_25 | DIFF_TERM = TRUE;
TIMESPEC TS_sysclk = PERIOD tnm_sysclk 200MHz;
#NET Reset_i LOC=F3; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET leds_o<0> LOC=D17 | IOSTANDARD=LVCMOS25;
NET leds_o<1> LOC=AB4 | IOSTANDARD=LVCMOS25;
NET leds_o<2> LOC=D21 | IOSTANDARD=LVCMOS25;
NET leds_o<3> LOC=W15 | IOSTANDARD=LVCMOS25;
NET dip_switch_i<0> LOC=C18;
NET dip_switch_i<1> LOC=Y6;
NET dip_switch_i<2> LOC=W6;
NET dip_switch_i<3> LOC=E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx=PADS("gmii_tx*");
TIMEGRP TG_gmii_tx OFFSET = OUT AFTER sysclk_p_i REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
#NET i2c_scl_io LOC=P11 | IOSTANDARD=LVCMOS25;
#NET i2c_sda_io LOC=N10 | IOSTANDARD=LVCMOS25;
NET "I2C_SDA_B" LOC = "R22"; ## C30 on FMC
NET "I2C_SCL_B" LOC = "T21"; ## C31 on FMC
#
# I/O to devices under test
NET "BUSY_P_I<0>" LOC = "D4"; ## "FMC_LA06_P" , C10 on FMC
NET "BUSY_N_I<0>" LOC = "D5"; ## "FMC_LA06_N" , C11 on FMC
NET "BUSY_P_I<1>" LOC = "AA16"; ## "FMC_LA28_P" , H31 on FMC
NET "BUSY_N_I<1>" LOC = "AB16"; ## "FMC_LA28_N" , H32 on FMC
NET "BUSY_P_I<2>" LOC = "B2"; ## "FMC_LA07_P" , H13 on FMC
NET "BUSY_N_I<2>" LOC = "A2"; ## "FMC_LA07_N" , H14 on FMC
NET "TRIGGERS_P_O<0>" LOC = "H10"; ## "FMC_LA10_P" , C14 on FMC
#NET "TRIGGERS_N_O<0>" LOC = "H11"; ## "FMC_LA10_N" , C15 on FMC
NET "TRIGGERS_P_O<1>" LOC = "W17"; ## "FMC_LA32_P" , H37 on FMC
#NET "TRIGGERS_N_O<1>" LOC = "Y18"; ## "FMC_LA32_N" , H38 on FMC
NET "TRIGGERS_P_O<2>" LOC = "F7"; ## "FMC_LA09_P" , D14 on FMC
#NET "TRIGGERS_N_O<2>" LOC = "F8"; ## "FMC_LA09_N" , D15 on FMC
#NET "SHUTTERS_P_O<0>" LOC = "R9"; ## "FMC_LA20_P" , G21 on FMC
#NET "SHUTTERS_N_O<0>" LOC = "R8"; ## "FMC_LA20_N" , G22 on FMC
#NET "SHUTTERS_P_O<1>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "SHUTTERS_N_O<1>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "SHUTTERS_P_O<2>" LOC = "R11"; ## "FMC_LA19_P" , H22 on FMC
#NET "SHUTTERS_N_O<2>" LOC = "T11"; ## "FMC_LA19_N" , H23 on FMC
NET "DUT_CLK_P_I<0>" LOC = "U16"; ## "FMC_LA31_P" , G33 on FMC , "DUT_CLK_P_I<0>
NET "DUT_CLK_N_I<0>" LOC = "V15"; ## "FMC_LA31_N" , G34 on FMC , DUT_CLK_N<0>
NET "DUT_CLK_P_I<1>" LOC = "AA14"; ## "FMC_LA24_P" , H28 on FMC , CONT_P<1>
NET "DUT_CLK_N_I<1>" LOC = "AB14"; ## "FMC_LA24_N" , H29 on FMC , CONT_N<1>
NET "DUT_CLK_P_I<2>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC , CONT_P<2>
NET "DUT_CLK_N_I<2>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC , CONT_N<2>
NET "RESET_OR_CLK_P_O<0>" LOC = "Y17"; ## "FMC_LA33_P" , G36 on FMC , CONT_P<0>
#NET "RESET_OR_CLK_N_O<0>" LOC = "AB17"; ## "FMC_LA33_N" , G37 on FMC , CONT_N<0>
NET "RESET_OR_CLK_P_O<1>" LOC = "V11"; ## "FMC_LA21_P" , H25 on FMC , CLK_P<1>
#NET "RESET_OR_CLK_N_O<1>" LOC = "W11"; ## "FMC_LA21_N" , H26 on FMC , CLK_QN<1>
NET "RESET_OR_CLK_P_O<2>" LOC = "C19"; ## "FMC_LA04_P" , H10 on FMC , CLK_P<2>
#NET "RESET_OR_CLK_N_O<2>" LOC = "A19"; ## "FMC_LA04_N" , H11 on FMC , CLK_N<2>
# Trigger inputs
# first constant-fraction-discrimiator comparator outputs
NET "CFD_DISCR_P_I<0>" LOC = "G9"; ## "FMC_LA00_CC_P" , G6 on FMC
NET "CFD_DISCR_N_I<0>" LOC = "F10"; ## "FMC_LA00_CC_N" , G7 on FMC
NET "CFD_DISCR_P_I<1>" LOC = "C17"; ## "FMC_LA14_P" , C18 on FMC
NET "CFD_DISCR_N_I<1>" LOC = "A17"; ## "FMC_LA14_N" , C19 on FMC
NET "CFD_DISCR_P_I<2>" LOC = "H13"; ## "FMC_LA12_P" , C22 on FMC
NET "CFD_DISCR_N_I<2>" LOC = "G13"; ## "FMC_LA12_N" , C23 on FMC
NET "CFD_DISCR_P_I<3>" LOC = "C5"; ## "FMC_LA16_P" , C26 on FMC
NET "CFD_DISCR_N_I<3>" LOC = "A5"; ## "FMC_LA16_N" , C27 on FMC
#NET "CFD_DISCR_P_I<2>" LOC = "T12"; ## "FMC_LA18_CC_P" , C22 on FMC
#NET "CFD_DISCR_N_I<2>" LOC = "U12"; ## "FMC_LA18_CC_N" , C23 on FMC
#NET "CFD_DISCR_P_I<3>" LOC = "AA10"; ## "FMC_LA27_P" , C26 on FMC
#NET "CFD_DISCR_N_I<3>" LOC = "AB10"; ## "FMC_LA27_N" , C27 on FMC
# then threshold comparator outputs
# N.B. These differ from v1 of schematics, since the original choice couldn't be routed.
NET "THRESHOLD_DISCR_P_I<0>" LOC = "F14"; ## "FMC_LA01_CC_P" , D8 on FMC
#NET "THRESHOLD_DISCR_N_I<0>" LOC = "F15"; ## "FMC_LA01_CC_N" , D9 on FMC
NET "THRESHOLD_DISCR_P_I<1>" LOC = "G16"; ## "FMC_LA13_P" , D17 on FMC
#NET "THRESHOLD_DISCR_N_I<1>" LOC = "F17"; ## "FMC_LA13_N" , D18 on FMC
NET "THRESHOLD_DISCR_P_I<2>" LOC = "D18"; ## "FMC_LA15_P" , H19 on FMC
#NET "THRESHOLD_DISCR_N_I<2>" LOC = "D19"; ## "FMC_LA15_N" , H20 on FMC
NET "THRESHOLD_DISCR_P_I<3>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
#NET "THRESHOLD_DISCR_N_I<3>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P<2>" LOC = "Y11"; ## "FMC_LA17_CC_P" , D20 on FMC
#NET "SPARE_N<2>" LOC = "AB11"; ## "FMC_LA17_CC_N" , D21 on FMC
#NET "SPARE_P<1>" LOC = "Y15"; ## "FMC_LA30_P" , H34 on FMC
#NET "SPARE_N<1>" LOC = "AB15"; ## "FMC_LA30_N" , H35 on FMC
NET "EXTCLK_P_B" LOC = "H12"; ## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "EXTCLK_N_B" LOC = "G11"; ## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
#NET "HDMI_POWER_ENABLE1" LOC = "G8"; ## "FMC_LA02_P" , H7 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA02_N" , H8 on FMC
firmware/ucf/sp605_FMC_mTLU_v1a.ucf
View file @ a2fd66ca
......@@ -21,7 +21,7 @@ TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET "I6/s_clk_is_xtal" TIG;
#NET "I6/s_clk_is_xtal" TIG;
NET "leds_o[0]" LOC = D17;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
......@@ -92,13 +92,13 @@ NET "busy_p_i[1]" LOC = C17; # mHDMI , J1
########### TRIGGER ##########################################
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = R9; # RJ45 , J3
#NET "triggers_p_o[0]" LOC = R9; # RJ45 , J3
## "FMC_LA16_P" , G18 on FMC
NET "triggers_p_o[2]" LOC = C5; # mHDMI , J2
#NET "triggers_p_o[2]" LOC = C5; # mHDMI , J2
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[1]" LOC = B18; # mHDMI , J1
#NET "triggers_p_o[1]" LOC = B18; # mHDMI , J1
########### SPARE #############################################
......@@ -106,12 +106,12 @@ NET "triggers_p_o[1]" LOC = B18; # mHDMI , J1
#NET "SPARE_P_O<1>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
#NET "shutter_to_dut_n_o[1]" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
#NET "shutter_to_dut_p_o[1]" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
NET "shutter_to_dut_p_o[1]" LOC = "T12"; ## "FMC_LA18_P" , C22 on FMC # mHDMI , J1
#NET "shutter_to_dut_p_o[1]" LOC = "T12"; ## "FMC_LA18_P" , C22 on FMC # mHDMI , J1
# Connector J2 used by TPix connection
#NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
NET "shutter_to_dut_p_o[2]" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC # mHDMI , J2
#NET "shutter_to_dut_p_o[2]" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC # mHDMI , J2
############ DUT_CLK ###########################################
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
......@@ -127,14 +127,14 @@ NET "dut_clk_p_o[2]" LOC = G8; # mHDMI , J2
############# CONT ##############################################
# Labelled CONT on schematic.
## "FMC_LA22_P" , G24 on FMC
NET "reset_or_clk_p_o[0]" LOC = V7; # RJ45 , J3
#NET "reset_or_clk_p_o[0]" LOC = V7; # RJ45 , J3
## "FMC_LA18_P" , C22 on FMC
#NET "reset_or_clk_p_o[1]" LOC = T12; # mHDMI , J1
NET "reset_or_clk_p_o[1]" LOC = B20; # "FMC_LA08_P" , G12 on FMC , mHDMI , J1
#NET "reset_or_clk_p_o[1]" LOC = B20; # "FMC_LA08_P" , G12 on FMC , mHDMI , J1
## "FMC_LA07_CC_P" , H13 on FMC
NET "reset_or_clk_p_o[2]" LOC = B2; # "FMC_LA07_CC_P" , H13 on FMC , mHDMI , J2
#NET "reset_or_clk_p_o[2]" LOC = B2; # "FMC_LA07_CC_P" , H13 on FMC , mHDMI , J2
......
firmware/ucf/sp605_FMC_mTLU_v1a_pintest.ucf deleted 100644 → 0
View file @ 6f62ad1c
#
# UCF for version 1a of updated mini-TLU
#
NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
NET "sysclk_p_i" LOC = K21;
NET "sysclk_p_i" IOSTANDARD = LVDS_25;
NET "sysclk_p_i" DIFF_TERM = "TRUE";
NET "sysclk_n_i" LOC = K22;
NET "sysclk_n_i" IOSTANDARD = LVDS_25;
NET "sysclk_n_i" DIFF_TERM = "TRUE";
TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
#NET "I6/s_clk_is_xtal" TIG;
NET "leds_o[0]" LOC = D17;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" LOC = AB4;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" LOC = D21;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" LOC = W15;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "dip_switch_i[0]" LOC = C18;
NET "dip_switch_i[1]" LOC = Y6;
NET "dip_switch_i[2]" LOC = W6;
NET "dip_switch_i[3]" LOC = E4;
# Ethernet PHY
# Main I2C bus
## C30 on FMC
NET "i2c_scl_b" LOC = T21;
## C31 on FMC
NET "i2c_sda_b" LOC = R22;
#
# I/O to devices under test
## "FMC_LA19_P" , H22 on FMC
NET "busy_p_o[0]" LOC = R11;
## "FMC_LA12_P" , G15 on FMC
NET "busy_p_o[1]" LOC = H13;
## "FMC_LA14_P" , C18 on FMC
NET "busy_p_o[2]" LOC = C17;
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = R9;
## "FMC_LA16_P" , G18 on FMC
NET "triggers_p_o[1]" LOC = C5;
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[2]" LOC = B18;
# Remove shutters ( also known as SPARE ) for now
NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
NET "SPARE_P_O<1>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
## "FMC_LA27_P" , C26 on FMC
NET "dut_clk_p_o[0]" LOC = AA10;
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_o[1]" LOC = V11;
## "FMC_LA02_P" , H7 on FMC
NET "dut_clk_p_o[2]" LOC = G8;
# Labelled CONT on schematic.
## "FMC_LA22_P" , G24 on FMC
NET "reset_or_clk_p_o[0]" LOC = V7;
## "FMC_LA07_CC_P" , H13 on FMC
NET "reset_or_clk_p_o[1]" LOC = B2;
## "FMC_LA18_P" , C22 on FMC
NET "reset_or_clk_p_o[2]" LOC = T12;
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
## "FMC_LA32_N" , H38 on FMC
NET "cfd_discr_n_i[0]" LOC = Y18;
## "FMC_LA30_N" , H35 on FMC
NET "cfd_discr_n_i[1]" LOC = AB15;
## "FMC_LA28_N" , H32 on FMC
NET "cfd_discr_n_i[2]" LOC = AB16;
## "FMC_LA24_N" , H29 on FMC
NET "cfd_discr_n_i[3]" LOC = AB14;
## "FMC_LA32_P" , H37 on FMC
NET "cfd_discr_p_i[0]" LOC = W17;
## "FMC_LA30_P" , H34 on FMC
NET "cfd_discr_p_i[1]" LOC = Y15;
## "FMC_LA28_P" , H31 on FMC
NET "cfd_discr_p_i[2]" LOC = AA16;
## "FMC_LA24_P" , H28 on FMC
NET "cfd_discr_p_i[3]" LOC = AA14;
# Threshold comparator outputs
## "FMC_LA33_N" , G37 on FMC
NET "threshold_discr_n_i[0]" LOC = AB17;
## "FMC_LA31_N" , G34 on FMC
NET "threshold_discr_n_i[1]" LOC = V15;
## "FMC_LA29_N" , G31 on FMC
NET "threshold_discr_n_i[2]" LOC = U15;
## "FMC_LA25_N" , G28 on FMC
NET "threshold_discr_n_i[3]" LOC = Y14;
## "FMC_LA33_P" , G36 on FMC
NET "threshold_discr_p_i[0]" LOC = Y17;
## "FMC_LA31_P" , G33 on FMC
NET "threshold_discr_p_i[1]" LOC = U16;
## "FMC_LA29_P" , G30 on FMC
NET "threshold_discr_p_i[2]" LOC = T15;
## "FMC_LA25_P" , G27 on FMC
NET "threshold_discr_p_i[3]" LOC = W14;
############
# External clock pins
## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "extclk_p_o" LOC = H12;
## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
NET "extclk_n_o" LOC = G11;
#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
## GPIO pins for debugging.
### 1 on J13 (thru series R100 200 ohm)
#NET "gpio_hdr[0]" LOC = N17;
### 3 on J13 (thru series R102 200 ohm)
#NET "gpio_hdr[1]" LOC = M18;
### 5 on J13 (thru series R101 200 ohm)
#NET "gpio_hdr[2]" LOC = A3;
### 7 on J13 (thru series R103 200 ohm)
#NET "gpio_hdr[3]" LOC = L15;
### 2 on J13 (thru series R99 200 ohm)
#NET "gpio_hdr[4]" LOC = F15;
### 4 on J13 (thru series R98 200 ohm)
#NET "gpio_hdr[5]" LOC = B4;
### 6 on J13 (thru series R97 200 ohm)
#NET "gpio_hdr[6]" LOC = F13;
### 8 on J13 (thru series R96 20
#NET "gpio_hdr[7]" LOC = P12;
firmware/ucf/sp605_FMC_mTLU_v1a_tpixJ2.ucf deleted 100644 → 0
View file @ 6f62ad1c
#
# UCF for version 1a of updated mini-TLU
#
NET "sysclk_p_i" TNM_NET = "tnm_sysclk";
NET "sysclk_p_i" LOC = K21;
NET "sysclk_p_i" IOSTANDARD = LVDS_25;
NET "sysclk_p_i" DIFF_TERM = "TRUE";
NET "sysclk_n_i" LOC = K22;
NET "sysclk_n_i" IOSTANDARD = LVDS_25;
NET "sysclk_n_i" DIFF_TERM = "TRUE";
TIMESPEC TS_sysclk = PERIOD "tnm_sysclk" 200 MHz;
# remove for now
#NET Reset_i LOC=P4; ## Global Reset
#NET ipb_clk TNM_NET = tnm_ipb_clk;
#NET clk125 TNM_NET = tnm_clk125;
#TIMESPEC TS_tig_ipb_125 = FROM tnm_ipb_clk TO tnm_clk125 TIG;
#TIMESPEC TS_tig_125_ipb = FROM tnm_clk125 TO tnm_ipb_clk TIG;
# NET clocks/rst* TIG;
NET "I6/s_clk_is_xtal" TIG;
NET "leds_o[0]" LOC = D17;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" LOC = AB4;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" LOC = D21;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" LOC = W15;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "dip_switch_i[0]" LOC = C18;
NET "dip_switch_i[1]" LOC = Y6;
NET "dip_switch_i[2]" LOC = W6;
NET "dip_switch_i[3]" LOC = E4;
# Ethernet PHY
TIMEGRP TG_gmii_tx = PADS("gmii_tx*");
TIMEGRP "TG_gmii_tx" OFFSET = OUT AFTER "sysclk_p_i" REFERENCE_PIN "gmii_gtx_clk_o" RISING;
NET gmii_gtx_clk_o LOC=AB7 |IOSTANDARD=LVCMOS25 | SLEW=FAST;
NET gmii_txd_o<0> LOC=U10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<1> LOC=T10 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<2> LOC=AB8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<3> LOC=AA8 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<4> LOC=AB9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<5> LOC=Y9 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<6> LOC=Y12 |IOSTANDARD=LVCMOS25;
NET gmii_txd_o<7> LOC=W12 |IOSTANDARD=LVCMOS25;
NET gmii_tx_en_o LOC=T8 |IOSTANDARD=LVCMOS25;
NET gmii_tx_er_o LOC=U8 |IOSTANDARD=LVCMOS25;
NET gmii_rx_clk_i LOC=P20 |IOSTANDARD=LVCMOS25 |TNM_NET= "gmii_rx_clk";
TIMESPEC "TS_GMII_RX_CLK_I" = PERIOD "gmii_rx_clk_i" 125MHz;
OFFSET = IN 2.5ns VALID 3ns BEFORE gmii_rx_clk_i;
NET gmii_rxd_i<0> LOC=P19 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<1> LOC=Y22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<2> LOC=Y21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<3> LOC=W22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<4> LOC=W20 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<5> LOC=V22 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<6> LOC=V21 |IOSTANDARD=LVCMOS25;
NET gmii_rxd_i<7> LOC=U22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_dv_i LOC=T22 |IOSTANDARD=LVCMOS25;
NET gmii_rx_er_i LOC=U20 |IOSTANDARD=LVCMOS25;
NET phy_rstb_o LOC=J22 |IOSTANDARD=LVCMOS25;
# Main I2C bus
## C30 on FMC
NET "i2c_scl_b" LOC = T21;
## C31 on FMC
NET "i2c_sda_b" LOC = R22;
#
# I/O to devices under test
############ BUSY ############################################
## "FMC_LA19_P" , H22 on FMC
NET "busy_p_i[0]" LOC = R11; # RJ45 , J3
## "FMC_LA12_P" , G15 on FMC
#NET "busy_p_i[2]" LOC = H13;
NET "T0_p_i" LOC = H13; # mHDMI , J2 , Now connected to TPix Telescope
## "FMC_LA14_P" , C18 on FMC
NET "busy_p_i[1]" LOC = C17; # mHDMI , J1
########### TRIGGER ##########################################
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = R9; # RJ45 , J3
## "FMC_LA16_P" , G18 on FMC
# NET "triggers_p_o[2]" LOC = C5; # mHDMI , J2 , Now connected to TPix Telescope
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[1]" LOC = B18; # mHDMI , J1
########### SPARE #############################################
#NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
#NET "SPARE_P_O<1>" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
#NET "shutter_to_dut_n_o[1]" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
#NET "shutter_to_dut_p_o[1]" LOC = "B20"; ## "FMC_LA08_P" , G12 on FMC
NET "shutter_to_dut_p_o[1]" LOC = "T12"; ## "FMC_LA18_P" , C22 on FMC # mHDMI , J1
# Connector J2 used by TPix connection
#NET "SPARE_N_O<2>" LOC = "G15"; ## "FMC_LA11_N" , H17 on FMC
#NET "SPARE_P_O<2>" LOC = "H14"; ## "FMC_LA11_P" , H16 on FMC
############ DUT_CLK ###########################################
# Labelled DUT_CLK on schematic for RJ45, CLK on HDMI
## "FMC_LA27_P" , C26 on FMC
NET "dut_clk_p_o[1]" LOC = AA10; # mHDMI , J1
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_o[0]" LOC = V11; # RJ45 , J3
## "FMC_LA02_P" , H7 on FMC
# NET "dut_clk_p_o[2]" LOC = G8; # mHDMI , J2 , connected to TPix 3 telescope
############# CONT ##############################################
# Labelled CONT on schematic.
## "FMC_LA22_P" , G24 on FMC
NET "reset_or_clk_p_o[0]" LOC = V7; # RJ45 , J3
## "FMC_LA18_P" , C22 on FMC
#NET "reset_or_clk_p_o[1]" LOC = T12; # mHDMI , J1
NET "reset_or_clk_p_o[1]" LOC = B20; # "FMC_LA08_P" , G12 on FMC , mHDMI , J1
## "FMC_LA07_CC_P" , H13 on FMC
# NET "reset_or_clk_p_o[2]" LOC = B2;
NET "TPix_Shutter_p_i" LOC = B2; # mHDMI , J2 , connected to TPix 3 telescope
##################################################################
# Trigger Inputs
# Constant-fraction-discrimiator comparator outputs
## "FMC_LA32_N" , H38 on FMC
NET "cfd_discr_n_i[0]" LOC = Y18;
## "FMC_LA30_N" , H35 on FMC
NET "cfd_discr_n_i[1]" LOC = AB15;
## "FMC_LA28_N" , H32 on FMC
NET "cfd_discr_n_i[2]" LOC = AB16;
## "FMC_LA24_N" , H29 on FMC
NET "cfd_discr_n_i[3]" LOC = AB14;
## "FMC_LA32_P" , H37 on FMC
NET "cfd_discr_p_i[0]" LOC = W17;
## "FMC_LA30_P" , H34 on FMC
NET "cfd_discr_p_i[1]" LOC = Y15;
## "FMC_LA28_P" , H31 on FMC
NET "cfd_discr_p_i[2]" LOC = AA16;
## "FMC_LA24_P" , H28 on FMC
NET "cfd_discr_p_i[3]" LOC = AA14;
# Threshold comparator outputs
## "FMC_LA33_N" , G37 on FMC
NET "threshold_discr_n_i[0]" LOC = AB17;
## "FMC_LA31_N" , G34 on FMC
NET "threshold_discr_n_i[1]" LOC = V15;
## "FMC_LA29_N" , G31 on FMC
NET "threshold_discr_n_i[2]" LOC = U15;
## "FMC_LA25_N" , G28 on FMC
NET "threshold_discr_n_i[3]" LOC = Y14;
## "FMC_LA33_P" , G36 on FMC
NET "threshold_discr_p_i[0]" LOC = Y17;
## "FMC_LA31_P" , G33 on FMC
NET "threshold_discr_p_i[1]" LOC = U16;
## "FMC_LA29_P" , G30 on FMC
NET "threshold_discr_p_i[2]" LOC = T15;
## "FMC_LA25_P" , G27 on FMC
NET "threshold_discr_p_i[3]" LOC = W14;
############
# External clock pins
## "FMC_CLK0_M2C_P" , H4 on FMC , "FRONT_PANEL_CLK_P"
NET "extclk_p_b" LOC = H12;
## "FMC_CLK0_M2C_N" , H5 on FMC , "FRONT_PANEL_CLK_N"
NET "extclk_n_b" LOC = G11;
#NET "HDMI_POWER_ENABLE1" LOC = "B16"; ## "FMC_LA04_P" , H10 on FMC
#NET "HDMI_POWER_ENABLE2" LOC = "F9"; ## "FMC_LA15_N" , H20 on FMC
## SP605 GPIO header.
NET "gpio_hdr[0]" LOC = "G7"; ## 1 on U52 (level shifter, U52.20 <-> GPIO_HEADER_0 <-> series R280 200 ohm <-> 1 on J55
NET "gpio_hdr[1]" LOC = "H6"; ## 3 on U52 (level shifter, U52.18 <-> GPIO_HEADER_0 <-> series R281 200 ohm <-> 2 on J55
NET "gpio_hdr[2]" LOC = "D1"; ## 4 on U52 (level shifter, U52.17 <-> GPIO_HEADER_0 <-> series R282 200 ohm <-> 3 on J55
NET "gpio_hdr[3]" LOC = "R7"; ## 5 on U52 (level shifter, U52.16 <-> GPIO_HEADER_0 <-> series R283 200 ohm <-> 4 on J55
## GPIO pins for debugging.
### 1 on J13 (thru series R100 200 ohm)
#NET "gpio_hdr[0]" LOC = N17;
### 3 on J13 (thru series R102 200 ohm)
#NET "gpio_hdr[1]" LOC = M18;
### 5 on J13 (thru series R101 200 ohm)
#NET "gpio_hdr[2]" LOC = A3;
### 7 on J13 (thru series R103 200 ohm)
#NET "gpio_hdr[3]" LOC = L15;
### 2 on J13 (thru series R99 200 ohm)
#NET "gpio_hdr[4]" LOC = F15;
### 4 on J13 (thru series R98 200 ohm)
#NET "gpio_hdr[5]" LOC = B4;
### 6 on J13 (thru series R97 200 ohm)
#NET "gpio_hdr[6]" LOC = F13;
### 8 on J13 (thru series R96 20
#NET "gpio_hdr[7]" LOC = P12;
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