Untested firmware to include IPBus register and synchronization

88d38344 · David Cussans · cd6d32d4 · 88d38344 · 88d38344 · 88d38344
Commit 88d38344 authored Sep 11, 2015 by David Cussans
3 changed files
--- a/firmware/hdl/common/sychronizedIPBusCtrlRegV_rtl.vhd
+++ b/firmware/hdl/common/sychronizedIPBusCtrlRegV_rtl.vhd
+--=============================================================================
+--! @file 
+--=============================================================================
+--
+-------------------------------------------------------------------------------
+-- --
+-- University of Bristol, High Energy Physics Group.
+-- --
+------------------------------------------------------------------------------- --
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+USE work.ipbus.all;
+use work.ipbus_reg_types.all;
+
+--! @brief IPBus registers synchronzied onto logic clock
+--!
+--! @details Uses DMN ipbus_ctrlreg_v - originally tried to use
+--! ipbus_ctrlreg_sync, but had poor results and added own synchronzier.
+
+entity synchronizedIPBusCtrlRegV_rtl is
+	generic(
+		N_CTRL: positive := 1;
+		N_STAT: positive := 1
+	);
+	port(
+		ipbus_clk_i: in std_logic;
+		ipbus_reset_i: in std_logic;
+		ipbus_i: in ipb_wbus;
+		ipbus_o: out ipb_rbus;
+                logic_clk_i: in std_logic;
+		status_to_ipbus_i: in ipb_reg_v(N_STAT - 1 downto 0); --! Synchronized to logic_clk_i       
+		sync_control_from_ipbus_o: out ipb_reg_v(N_CTRL - 1 downto 0); --! Synchronized to logic_clk_i
+		stb_o: out std_logic_vector(N_CTRL - 1 downto 0) --! high when change made to a control register. Broken ( needs to be retimed )
+	);
+	
+end synchronizedIPBusCtrlRegV_rtl;
+
+
+architecture rtl of synchronizedIPBusCtrlRegV_rtl is
+
+  signal s_sync_status_to_ipbus : ipb_reg_v(c_N_STAT-1 downto 0);
+  signal s_control_from_ipbus   : ipb_reg_v(c_N_CTRL-1 downto 0);
+ 
+begin  -- architecture rtl
+
+  
+  ipbus_registers: entity work.ipbus_ctrlreg_v
+    generic map(
+      N_CTRL => c_N_CTRL,
+      N_STAT => c_N_STAT
+      )
+    port map(
+      clk => ipbus_clk_i,
+      reset=> ipbus_reset_i ,
+      ipbus_in=>  ipbus_i,
+      ipbus_out=> ipbus_o,
+      d=>  s_sync_status_to_ipbus,
+      q=>  s_control_from_ipbus,
+      stb=>  stb_o
+      );
+
+  -- Synchronize registers from logic clock to ipbus.
+    sync_status: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_STAT )
+    port map (
+      clk_input_i => clk_4x_logic_i,
+      data_i      =>  status_to_ipbus_i,
+      data_o      => s_sync_status_to_ipbus,
+      clk_output_i => ipbus_clk_i);
+
+    -- Synchronize registers from logic clock to ipbus.
+    sync_ctrl: entity work.synchronizeRegisters
+    generic map (
+      g_NUM_REGISTERS => c_N_CTRL )
+    port map (
+      clk_input_i => ipbus_clk_i,
+      data_i      =>  s_control_from_ipbus,
+      data_o      => sync_control_from_ipbus_o,
+      clk_output_i => clk_4x_logic_i);
+
+end architecture rtl;
--- a/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat
+++ b/firmware/hdl_designer/fmc_mTLU/fmc_mTLU_lib/hds/.cache.dat
--- a/firmware/scripts/test_aida_tlu_internal_triggers_v2.py
+++ b/firmware/scripts/test_aida_tlu_internal_triggers_v2.py
@@ -17,8 +17,8 @@ bAddrTab = AddressTable("./aida_mini_tlu_addr_map.txt")
 board = ChipsBusUdp(bAddrTab,"192.168.200.32",50001)

 # Check the bus for I2C devices
-#executeI2C = True
-executeI2C = False
+executeI2C = True
+#executeI2C = False
 if executeI2C:
    boardi2c = FmcTluI2c(board)
    boardId = boardi2c.get_serial_number()