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AIDA-2020 TLU
Commit a2e74625 authored by David Cussans's avatar David Cussans
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Passes synthesis , Map and P&R

parent 4963713a
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firmware/hdl/common/TPx3_iface.vhd
View file @ a2e74625
--! Simple module to interface AIDA TLU to LHCb TimePix3 telescope.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
library unisim;
use unisim.VComponents.all;
entity TPx3_iface is
port (
......@@ -12,8 +19,51 @@ end entity TPx3_iface;
architecture rtl of TPx3_iface is
signal s_T0 , s_T0_d1 , s_T0_d2 , s_stretch_T0_in: std_logic := '0'; -- signal after IBufDS and sampled onto clk_4x
signal s_stretch_T0_in_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by T0ger_i
signal s_T0_out_sr : std_logic_vector(2 downto 0) := "111"; --! Gets shifted out by clk_4x logic. Loaded by strobe_4x_logic
begin -- architecture rtl
cmp_IBUFDS_T0 : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => s_T0, -- Buffer output
I => T0_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => T0_n_i -- Diff_n buffer input (connect directly to top-level port)
);
p_T0_retime: process (clk_4x_i , clk_4x_strobe , s_T0) is
begin -- process p_T0_retime
if rising_edge(clk_4x_i) then
s_T0_d1 <= s_T0;
s_T0_d2 <= s_T0_d1;
-- Stretch T0ger_i pulse to 4 clock cycles on clk4x
if s_T0_d1 = '1' then
s_stretch_T0_in <= '1';
s_stretch_T0_in_sr <= "111";
else
s_stretch_T0_in <= s_stretch_T0_in_sr(0);
s_stretch_T0_in_sr <= '0' & s_stretch_T0_in_sr(s_stretch_T0_in_sr'left downto 1);
end if;
--
if (clk_4x_strobe = '1') and ( s_stretch_T0_in = '1' ) then
T0_o <= '1';
s_T0_out_sr <= "111";
else
T0_o <= s_T0_out_sr(0);
s_T0_out_sr <= '0' & s_T0_out_sr(s_T0_out_sr'left downto 1);
end if;
end if;
end process p_T0_retime;
end architecture rtl;
firmware/hdl/common/logic_clocks_rtl.vhd
View file @ a2e74625
......@@ -103,7 +103,9 @@ ARCHITECTURE rtl OF logic_clocks IS
-- Eventually connect up clock control & status lines to IPBus
--signal s_extclk_is_input : std_logic := '0';
-- signal s_extclk_is_input_buf : std_logic := '1';
signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '1';
-- signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '1';
signal s_clk_is_xtal, s_clk_is_ext_buf : std_logic := '0'; -- default to
-- input from ext
-- signal s_logic_clk_rst : std_logic := '0';
signal s_locked_pll, s_locked_bufpll : std_logic;
......@@ -197,17 +199,27 @@ BEGIN
logic_clocks_locked_o <= s_locked_bufpll and s_locked_pll;
ext_clk_obuf : IOBUFDS
generic map (
IOSTANDARD => "BLVDS_25")
port map (
O => s_extclk, -- Buffer output
IO => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
IOB => extclk_n_b, -- Diff_n inout (connect directly to top-level port)
I => s_DUT_Clk_o, -- Buffer input
T => s_clk_is_ext_buf -- 3-state enable input, high=input, low=output
);
--ext_clk_obuf : IOBUFDS
--generic map (
-- IOSTANDARD => "BLVDS_25")
--port map (
-- O => s_extclk, -- Buffer output
-- IO => extclk_p_b, -- Diff_p inout (connect directly to top-level port)
-- IOB => extclk_n_b, -- Diff_n inout (connect directly to top-level port)
-- I => s_DUT_Clk_o, -- Buffer input
-- T => s_clk_is_ext_buf -- 3-state enable input, high=input, low=output
--);
cmp_IBUFDS_extclk : IBUFDS
generic map (
DIFF_TERM => TRUE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "LVDS_25")
port map (
O => s_extclk, -- Buffer output
I => extclk_p_b, -- Diff_p buffer input (connect directly to top-level port)
IB => extclk_p_b -- Diff_n buffer input (connect directly to top-level port)
);
ddr_for_extclk_output : ODDR2
generic map(
......@@ -246,16 +258,17 @@ BEGIN
--! Clock selection
clock_mux : BUFGMUX
generic map (
CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
)
port map (
O => s_DUT_Clk, -- 1-bit output: Clock buffer output
I0 => s_extclkG, -- 1-bit input: Clock buffer input (S=0)
I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
S => s_clk_is_xtal -- 1-bit input: Clock buffer select
);
--clock_mux : BUFGMUX
-- generic map (
-- CLK_SEL_TYPE => "SYNC" -- Glitchles ("SYNC") or fast ("ASYNC") clock switch-over
-- )
-- port map (
-- O => s_DUT_Clk, -- 1-bit output: Clock buffer output
-- I0 => s_extclkG, -- 1-bit input: Clock buffer input (S=0)
-- I1 => clk_logic_xtal_i, -- 1-bit input: Clock buffer input (S=1)
-- S => s_clk_is_xtal -- 1-bit input: Clock buffer select
-- );
s_DUT_Clk <= s_extclkG; -- Hard wire for now.
extclk_buf : BUFG
port map(
......
firmware/ucf/sp605_FMC_mTLU_v1a.ucf
View file @ a2e74625
......@@ -84,14 +84,16 @@ NET "busy_p_i[0]" LOC = R11;
## "FMC_LA12_P" , G15 on FMC
NET "busy_p_i[1]" LOC = H13;
## "FMC_LA14_P" , C18 on FMC
NET "busy_p_i[2]" LOC = C17;
# Hack to communicate with TPix3 telescope
#NET "busy_p_i[2]" LOC = C17;
## "FMC_LA20_P" , G21 on FMC
NET "triggers_p_o[0]" LOC = R9;
## "FMC_LA16_P" , G18 on FMC
NET "triggers_p_o[1]" LOC = C5;
## "FMC_LA03_P" , G9 on FMC
NET "triggers_p_o[2]" LOC = B18;
# Hack to communicate with TPix3 telescope
#NET "triggers_p_o[2]" LOC = B18;
# Remove shutters ( also known as SPARE ) for now
#NET "SPARE_N_O<1>" LOC = "A20"; ## "FMC_LA08_N" , G13 on FMC
......@@ -105,7 +107,8 @@ NET "dut_clk_p_o[0]" LOC = AA10;
## "FMC_LA21_P" , H25 on FMC
NET "dut_clk_p_o[1]" LOC = V11;
## "FMC_LA02_P" , H7 on FMC
NET "dut_clk_p_o[2]" LOC = G8;
# Hack to communicate with TPix3 telescope
#NET "dut_clk_p_o[2]" LOC = G8;
# Labelled CONT on schematic.
......@@ -114,7 +117,9 @@ NET "reset_or_clk_p_o[0]" LOC = V7;
## "FMC_LA07_CC_P" , H13 on FMC
NET "reset_or_clk_p_o[1]" LOC = B2;
## "FMC_LA18_P" , C22 on FMC
NET "reset_or_clk_p_o[2]" LOC = T12;
# Hack to communicate with TPix3 telescope
#D NET "reset_or_clk_p_o[2]" LOC = T12;
NET "T0_p_i" LOC = T12;
# Trigger Inputs
......
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