platform/xilinx: don't constrain clock frequencies in the GTHE4 XDC file, they are already set in the top level XDC

modules/wr_streamers: make DBG_WORD optional (generic parameter). Remove MARK_DEBUG attributes to facilitate timing closure

- REQUIRES V5 DEV BRANCH WRPC-SW
- syscon diag registers (read-write) are now remapped at offset (periph + 0x900)
- user diag registers are at the previous address (periph + 0x800), keeping the legacy layout
- the new scheme uses much less FF/LUT resources and allows adding arbitrary diagnostics without affecting the SYSCON layout or HDL modifications

wr_core: allow to select legacy (128kB)/increased (256kB) LM32 RAM address space. Default is 128kB (legacy)

platform/xilinx: split platform for vivado to a separate file not to break ise build with unknown primitives

wr_gthe3_phy_family7: assert rx_enc_err when the link is down to reliably force link down event in the PCS