built from commit 5eeb579d in wrpc-sw repo

Otherwise we do twice the same write to memory and we permanently lose one
nrx_avail. This way, after some time minic may drop frames because it will think
its buffer has not enough space (based on nrx_avail value).

Not needed since the time we have a t24p measurement procedure.

Register stores new fields that were added to MCR since MDIO regs can be only
16-bits.

added delta delays in phy output signals to line up with the ch#_rx_rbclk_o assignment (purely necessary for proper simulation only)

when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the U_TX_FIFO to empty in order to catch the proper timestamp for the oob signalled packet.

Sometimes *.wb file had to be updated to produce the same result as used till
now. Earlier wbgen2 had a problem accepting _align_ for the first field in a
register. The bug was fixed, but we want to keep the alignment the old way
(already used in the software). Hence I had to delete some of the _align_
directives.

added tx_prbs_sel, sfp_tx_disable, sfp_loss, sfp_tx_fault and full width loopback to MDIO Control register. Be careful: Single bit loopback was relocated to accomodate loopback(2:0)!

Otherwise, hdlmake complains.

modules/endpoint: count rx frames at the end of rx_path chain and let wr_endpoint decide which one to export

It was usefull when debugging the SWcore on high traffic load.

When rx buffer is full when new SOF arrives, the whole frame is dropped and not
stored in the buffer. However, RTU request was still generated by the
ep_rtu_header_extract.
This patch prevents ep_rtu_header_extract from generating rtu request, when
rxbuf is full on SOF.

phy_rdy_i was needed to fix the Virtex-6 FIFO reseting issue on the WRS.
However, WRPC uses inferred fifo which has fully asynchronous reset and does not
suffer from this bug. Therefore in case of the WRPC this signal can be tied to
'1' or drived from the GTP serdes.

Earlier we were resetting clock alignment fifo (ep_rx_path) when GTX was still
not locked and was not producing rx clock. Xilinx document ug363 (Virtex-6 FPGA
Memory Resources) says that dual-clock fifo should have reset signal asserted
for at least three clock cycles. Chipscope says our fifo was reset while rx
clock was not yet there. This apparently was causing Xilinx fifo block going
crazy once every few boots. As a result FIFO was asserting _empty_ and
_almost_full_ outputs at the same time causing the rx path to stall forever.

platform/xilinx: adding rdy_o to gtx and gtp wrappers to indicate when serdes is ready and produces rx clock