Skip to content

W
White Rabbit core collection
Commit 61879a3a authored by Peter Jansweijer's avatar Peter Jansweijer Committed by Grzegorz Daniluk
Browse files
Options

wrc_core: improve 8/16-bit PCS selection

parent 0a10e319
Hide whitespace changes
Inline Side-by-side
Showing with 97 additions and 125 deletions
modules/wr_endpoint/endpoint_pkg.vhd
View file @ 61879a3a
......@@ -43,6 +43,10 @@ use work.wr_fabric_pkg.all;
package endpoint_pkg is
function f_pcs_data_width(pcs_16 : boolean) return integer;
function f_pcs_k_width(pcs_16 : boolean) return integer;
function f_pcs_bts_width(pcs_16 : boolean) return integer;
type t_txtsu_timestamp is record
stb : std_logic;
tsval : std_logic_vector(31 downto 0);
......@@ -133,15 +137,15 @@ package endpoint_pkg is
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(15 downto 0);
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(15 downto 0) := x"0000";
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_clk_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(1 downto 0) := "00";
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(4 downto 0) := "00000";
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
gmii_tx_clk_i : in std_logic := '0';
gmii_txd_o : out std_logic_vector(7 downto 0);
gmii_tx_en_o : out std_logic;
......@@ -236,15 +240,15 @@ package endpoint_pkg is
phy_syncen_o : out std_logic;
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(15 downto 0);
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(15 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_clk_i : in std_logic;
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(4 downto 0);
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
gmii_tx_clk_i : in std_logic := '0';
gmii_txd_o : out std_logic_vector(7 downto 0) := x"00";
gmii_tx_en_o : out std_logic := '0';
......@@ -340,5 +344,36 @@ package endpoint_pkg is
end endpoint_pkg;
package body endpoint_pkg is
function f_pcs_data_width(pcs_16 : boolean)
return integer is
begin
if (pcs_16) then
return 16;
else
return 8;
end if;
end function;
function f_pcs_k_width(pcs_16 : boolean)
return integer is
begin
if (pcs_16) then
return 2;
else
return 1;
end if;
end function;
function f_pcs_bts_width(pcs_16 : boolean)
return integer is
begin
if (pcs_16) then
return 5;
else
return 4;
end if;
end function;
end package body endpoint_pkg;
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ 61879a3a
......@@ -145,15 +145,15 @@ package endpoint_private_pkg is
serdes_enable_o : out std_logic;
serdes_rdy_i : in std_logic;
serdes_tx_clk_i : in std_logic;
serdes_tx_data_o : out std_logic_vector(15 downto 0);
serdes_tx_k_o : out std_logic_vector(1 downto 0);
serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
serdes_tx_disparity_i : in std_logic;
serdes_tx_enc_err_i : in std_logic;
serdes_rx_clk_i : in std_logic;
serdes_rx_data_i : in std_logic_vector(15 downto 0);
serdes_rx_k_i : in std_logic_vector(1 downto 0);
serdes_rx_data_i : in std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
serdes_rx_k_i : in std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
serdes_rx_enc_err_i : in std_logic;
serdes_rx_bitslide_i : in std_logic_vector(4 downto 0);
serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
rmon_o : out t_rmon_triggers;
mdio_addr_i : in std_logic_vector(15 downto 0);
mdio_data_i : in std_logic_vector(15 downto 0);
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ 61879a3a
......@@ -160,11 +160,11 @@ entity ep_1000basex_pcs is
-- TX Code group. In 16-bit mode, the MSB is TXed first (tx_data_o[15:8],
-- then tx_data_o[7:0]). In 8-bit mode only bits [7:0] are used.
serdes_tx_data_o : out std_logic_vector(15 downto 0);
serdes_tx_data_o : out std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
-- TX Control Code: When 1, a K-character is transmitted. In 16-bit mode,
-- bit 1 goes first, in 8-bit mode only bit 0 is used.
serdes_tx_k_o : out std_logic_vector(1 downto 0);
serdes_tx_k_o : out std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
-- TX Disparity input: 1 = last transmitted code group ended with negative
-- running disparity, 0 = positive RD.
......@@ -181,10 +181,10 @@ entity ep_1000basex_pcs is
-- RX recovered clock. MUST be synchronous to incoming serial data stream
-- for proper PTP/SyncE operation. 62.5 MHz in 16-bit mode, 125 MHz in 8-bit mode.
serdes_rx_clk_i : in std_logic;
serdes_rx_data_i : in std_logic_vector(15 downto 0);
serdes_rx_k_i : in std_logic_vector(1 downto 0);
serdes_rx_data_i : in std_logic_vector(f_pcs_data_width(g_16bit)-1 downto 0);
serdes_rx_k_i : in std_logic_vector(f_pcs_k_width(g_16bit)-1 downto 0);
serdes_rx_enc_err_i : in std_logic;
serdes_rx_bitslide_i : in std_logic_vector(4 downto 0);
serdes_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_16bit)-1 downto 0);
-- RMON events, aligned to clk_sys
rmon_o : out t_rmon_triggers;
......@@ -333,6 +333,7 @@ begin -- rtl
nice_dbg_o => nice_dbg_o.rx
);
mdio_wr_spec_bslide <= serdes_rx_bitslide_i(4 downto 0);
end generate gen_16bit;
......@@ -362,10 +363,6 @@ begin -- rtl
phy_tx_enc_err_i => serdes_tx_enc_err_i
);
serdes_tx_k_o(1) <= 'X';
serdes_tx_data_o(15 downto 8) <= (others => 'X');
U_RX_PCS : ep_rx_pcs_8bit
generic map (
g_simulation => g_simulation)
......@@ -404,6 +401,8 @@ begin -- rtl
phy_rx_enc_err_i => serdes_rx_enc_err_i
);
mdio_wr_spec_bslide <= '0' & serdes_rx_bitslide_i(3 downto 0);
end generate gen_8bit;
txpcs_busy_o <= txpcs_busy_int;
......@@ -412,7 +411,6 @@ begin -- rtl
mdio_mcr_pdown <= mdio_mcr_pdown_cpu or (not link_ctr_i);
serdes_rst_o <= (not pcs_reset_n) or mdio_mcr_pdown;
mdio_wr_spec_bslide <= serdes_rx_bitslide_i(4 downto 0);
U_MDIO_WB : ep_pcs_tbi_mdio_wb
port map (
......
modules/wr_endpoint/wr_endpoint.vhd
View file @ 61879a3a
......@@ -117,16 +117,16 @@ entity wr_endpoint is
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(15 downto 0);
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(15 downto 0);
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_clk_i : in std_logic;
phy_rx_k_i : in std_logic_vector(1 downto 0);
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(4 downto 0);
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
-------------------------------------------------------------------------------
-- GMII Interface (8-bit)
......@@ -538,7 +538,7 @@ begin
serdes_rx_clk_i => phy_rx_clk_i,
serdes_rx_k_i => phy_rx_k_i,
serdes_rx_enc_err_i => phy_rx_enc_err_i,
serdes_rx_bitslide_i => phy_rx_bitslide_i(4 downto 0),
serdes_rx_bitslide_i => phy_rx_bitslide_i,
rmon_o => pcs_rmon,
......
modules/wr_endpoint/xwr_endpoint.vhd
View file @ 61879a3a
......@@ -106,16 +106,16 @@ entity xwr_endpoint is
phy_rdy_i : in std_logic;
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(15 downto 0);
phy_tx_k_o : out std_logic_vector(1 downto 0);
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(15 downto 0) := x"0000";
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_clk_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(1 downto 0) := "00";
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(4 downto 0) := "00000";
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
-------------------------------------------------------------------------------
-- GMII Interface (8-bit)
......
modules/wrc_core/wr_core.vhd
View file @ 61879a3a
......@@ -139,14 +139,13 @@ entity wr_core is
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_k16_o : out std_logic;
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_k16_i : in std_logic := '0';
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
......@@ -339,12 +338,6 @@ architecture struct of wr_core is
-----------------------------------------------------------------------------
--Endpoint
-----------------------------------------------------------------------------
signal phy_tx_data_int : std_logic_vector(15 downto 0);
signal phy_tx_k_int : std_logic_vector(1 downto 0);
signal phy_rx_data_int : std_logic_vector(15 downto 0);
signal phy_rx_k_int : std_logic_vector(1 downto 0);
signal phy_rx_bitslide_int : std_logic_vector(4 downto 0);
signal ep_txtsu_port_id : std_logic_vector(4 downto 0);
signal ep_txtsu_frame_id : std_logic_vector(15 downto 0);
signal ep_txtsu_ts_value : std_logic_vector(31 downto 0);
......@@ -609,25 +602,6 @@ begin
-----------------------------------------------------------------------------
-- Endpoint
-----------------------------------------------------------------------------
phy_tx_data_o <= phy_tx_data_int(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o <= phy_tx_k_int(0);
phy_rx_k_int(0) <= phy_rx_k_i;
gen_16bit_phy_if: if g_pcs_16bit generate
phy_tx_k16_o <= phy_tx_k_int(1);
phy_rx_data_int <= phy_rx_data_i;
phy_rx_k_int(1) <= phy_rx_k16_i;
phy_rx_bitslide_int <= phy_rx_bitslide_i;
end generate;
gen_8bit_phy_if: if not g_pcs_16bit generate
phy_tx_k16_o <= '0';
phy_rx_data_int <= x"00" & phy_rx_data_i;
phy_rx_k_int(1) <= '0';
phy_rx_bitslide_int <= '0' & phy_rx_bitslide_i;
end generate;
U_Endpoint : xwr_endpoint
generic map (
g_interface_mode => PIPELINED,
......@@ -663,15 +637,15 @@ begin
phy_sfp_los_i => phy_sfp_los_i,
phy_sfp_tx_disable_o => phy_sfp_tx_disable_o,
phy_ref_clk_i => phy_ref_clk_i,
phy_tx_data_o => phy_tx_data_int,
phy_tx_k_o => phy_tx_k_int,
phy_tx_data_o => phy_tx_data_o,
phy_tx_k_o => phy_tx_k_o,
phy_tx_disparity_i => phy_tx_disparity_i,
phy_tx_enc_err_i => phy_tx_enc_err_i,
phy_rx_data_i => phy_rx_data_int,
phy_rx_data_i => phy_rx_data_i,
phy_rx_clk_i => phy_rx_rbclk_i,
phy_rx_k_i => phy_rx_k_int,
phy_rx_k_i => phy_rx_k_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_int,
phy_rx_bitslide_i => phy_rx_bitslide_i,
src_o => ep_src_out,
src_i => ep_src_in,
......
modules/wrc_core/wrcore_pkg.vhd
View file @ 61879a3a
......@@ -11,9 +11,6 @@ use work.softpll_pkg.all;
package wrcore_pkg is
function f_pcs_data_width(pcs_16 : boolean) return integer;
function f_pcs_bts_width(pcs_16 : boolean) return integer;
-----------------------------------------------------------------------------
--PPS generator
-----------------------------------------------------------------------------
......@@ -313,15 +310,15 @@ package wrcore_pkg is
g_vuart_fifo_size : integer := 1024;
g_pcs_16bit : boolean := false);
port(
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic := '0';
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_mul_i: in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_dmtd_i : in std_logic := '0';
clk_ref_i : in std_logic;
clk_aux_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
clk_ext_mul_i : in std_logic := '0';
clk_ext_mul_locked_i : in std_logic := '1';
clk_ext_i : in std_logic := '0';
pps_ext_i : in std_logic := '0';
rst_n_i : in std_logic;
dac_hpll_load_p1_o : out std_logic;
dac_hpll_data_o : out std_logic_vector(15 downto 0);
......@@ -330,16 +327,14 @@ package wrcore_pkg is
phy_ref_clk_i : in std_logic := '0';
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_k16_o : out std_logic;
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_rbclk_i : in std_logic := '0';
phy_rx_k_i : in std_logic := '0';
phy_rx_k16_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rst_o : out std_logic;
phy_rdy_i : in std_logic := '1';
phy_loopen_o : out std_logic;
......@@ -467,15 +462,13 @@ package wrcore_pkg is
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_k16_o : out std_logic;
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic := '0';
phy_tx_enc_err_i : in std_logic := '0';
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
phy_rx_rbclk_i : in std_logic := '0';
phy_rx_k_i : in std_logic := '0';
phy_rx_k16_i : in std_logic := '0';
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0):= (others=>'0');
phy_rx_enc_err_i : in std_logic := '0';
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0) := (others=>'0');
......@@ -627,27 +620,3 @@ package wrcore_pkg is
end component;
end wrcore_pkg;
package body wrcore_pkg is
function f_pcs_data_width(pcs_16 : boolean)
return integer is
begin
if (pcs_16) then
return 16;
else
return 8;
end if;
end function;
function f_pcs_bts_width(pcs_16 : boolean)
return integer is
begin
if (pcs_16) then
return 5;
else
return 4;
end if;
end function;
end wrcore_pkg;
modules/wrc_core/xwr_core.vhd
View file @ 61879a3a
......@@ -123,15 +123,13 @@ entity xwr_core is
phy_ref_clk_i : in std_logic;
phy_tx_data_o : out std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_tx_k_o : out std_logic;
phy_tx_k16_o : out std_logic;
phy_tx_k_o : out std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_tx_disparity_i : in std_logic;
phy_tx_enc_err_i : in std_logic;
phy_rx_data_i : in std_logic_vector(f_pcs_data_width(g_pcs_16bit)-1 downto 0);
phy_rx_rbclk_i : in std_logic;
phy_rx_k_i : in std_logic;
phy_rx_k16_i : in std_logic;
phy_rx_k_i : in std_logic_vector(f_pcs_k_width(g_pcs_16bit)-1 downto 0);
phy_rx_enc_err_i : in std_logic;
phy_rx_bitslide_i : in std_logic_vector(f_pcs_bts_width(g_pcs_16bit)-1 downto 0);
......@@ -267,13 +265,11 @@ begin
phy_ref_clk_i => phy_ref_clk_i,
phy_tx_data_o => phy_tx_data_o,
phy_tx_k_o => phy_tx_k_o,
phy_tx_k16_o => phy_tx_k16_o,
phy_tx_disparity_i => phy_tx_disparity_i,
phy_tx_enc_err_i => phy_tx_enc_err_i,
phy_rx_data_i => phy_rx_data_i,
phy_rx_rbclk_i => phy_rx_rbclk_i,
phy_rx_k_i => phy_rx_k_i,
phy_rx_k16_i => phy_rx_k16_i,
phy_rx_enc_err_i => phy_rx_enc_err_i,
phy_rx_bitslide_i => phy_rx_bitslide_i,
phy_rst_o => phy_rst_o,
......
top/spec_1_1/wr_core_demo/spec_top.vhd
View file @ 61879a3a
......@@ -350,12 +350,12 @@ architecture rtl of spec_top is
signal pps_led : std_logic;
signal phy_tx_data : std_logic_vector(7 downto 0);
signal phy_tx_k : std_logic;
signal phy_tx_k : std_logic_vector(0 downto 0);
signal phy_tx_disparity : std_logic;
signal phy_tx_enc_err : std_logic;
signal phy_rx_data : std_logic_vector(7 downto 0);
signal phy_rx_rbclk : std_logic;
signal phy_rx_k : std_logic;
signal phy_rx_k : std_logic_vector(0 downto 0);
signal phy_rx_enc_err : std_logic;
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
......@@ -812,12 +812,12 @@ begin
ch1_ref_clk_i => clk_125m_pllref,
ch1_tx_data_i => phy_tx_data,
ch1_tx_k_i => phy_tx_k,
ch1_tx_k_i => phy_tx_k(0),
ch1_tx_disparity_o => phy_tx_disparity,
ch1_tx_enc_err_o => phy_tx_enc_err,
ch1_rx_data_o => phy_rx_data,
ch1_rx_rbclk_o => phy_rx_rbclk,
ch1_rx_k_o => phy_rx_k,
ch1_rx_k_o => phy_rx_k(0),
ch1_rx_enc_err_o => phy_rx_enc_err,
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment