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White Rabbit core collection
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White Rabbit core collection
Commits
5b9d66fc
Commit
5b9d66fc
authored
Aug 04, 2015
by
Peter Jansweijer
Committed by
Grzegorz Daniluk
Sep 01, 2015
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Plain Diff
wrc_core: bubble up tx pause control signals
parent
61879a3a
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3 changed files
with
32 additions
and
0 deletions
+32
-0
wr_core.vhd
modules/wrc_core/wr_core.vhd
+10
-0
wrcore_pkg.vhd
modules/wrc_core/wrcore_pkg.vhd
+11
-0
xwr_core.vhd
modules/wrc_core/xwr_core.vhd
+11
-0
No files found.
modules/wrc_core/wr_core.vhd
View file @
5b9d66fc
...
...
@@ -254,6 +254,13 @@ entity wr_core is
txtsu_stb_o
:
out
std_logic
;
txtsu_ack_i
:
in
std_logic
:
=
'1'
;
-----------------------------------------
-- Pause Frame Control
-----------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
-----------------------------------------
-- Timecode/Servo Control
-----------------------------------------
...
...
@@ -661,6 +668,9 @@ begin
wb_i
=>
ep_wb_in
,
wb_o
=>
ep_wb_out
,
rmon_events_o
=>
open
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
led_link_o
=>
ep_led_link
,
led_act_o
=>
led_act_o
);
...
...
modules/wrc_core/wrcore_pkg.vhd
View file @
5b9d66fc
...
...
@@ -383,6 +383,10 @@ package wrcore_pkg is
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
tm_link_up_o
:
out
std_logic
;
tm_dac_value_o
:
out
std_logic_vector
(
23
downto
0
);
tm_dac_wr_o
:
out
std_logic_vector
(
g_aux_clks
-1
downto
0
);
...
...
@@ -576,6 +580,13 @@ package wrcore_pkg is
txtsu_stb_o
:
out
std_logic
;
txtsu_ack_i
:
in
std_logic
:
=
'1'
;
-----------------------------------------
-- Pause Frame Control
-----------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
-----------------------------------------
-- Timecode/Servo Control
-----------------------------------------
...
...
modules/wrc_core/xwr_core.vhd
View file @
5b9d66fc
...
...
@@ -199,6 +199,13 @@ entity xwr_core is
timestamps_o
:
out
t_txtsu_timestamp
;
timestamps_ack_i
:
in
std_logic
:
=
'1'
;
-----------------------------------------
-- Pause Frame Control
-----------------------------------------
fc_tx_pause_req_i
:
in
std_logic
:
=
'0'
;
fc_tx_pause_delay_i
:
in
std_logic_vector
(
15
downto
0
)
:
=
x"0000"
;
fc_tx_pause_ready_o
:
out
std_logic
;
-----------------------------------------
-- Timecode/Servo Control
-----------------------------------------
...
...
@@ -354,6 +361,10 @@ begin
txtsu_stb_o
=>
timestamps_o
.
stb
,
txtsu_ack_i
=>
timestamps_ack_i
,
fc_tx_pause_req_i
=>
fc_tx_pause_req_i
,
fc_tx_pause_delay_i
=>
fc_tx_pause_delay_i
,
fc_tx_pause_ready_o
=>
fc_tx_pause_ready_o
,
tm_link_up_o
=>
tm_link_up_o
,
tm_dac_value_o
=>
tm_dac_value_o
,
tm_dac_wr_o
=>
tm_dac_wr_o
,
...
...
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