wrc_core: set g_ref_clock_rate based on pcs 8/16bit width

dc1a2f63 · Grzegorz Daniluk · 2da09bd3 · dc1a2f63 · dc1a2f63
Commit dc1a2f63 authored Sep 28, 2015 by Grzegorz Daniluk
Hide whitespace changes
Inline Side-by-side

Showing with 18 additions and 2 deletions

wr_core.vhd modules/wrc_core/wr_core.vhd +2 -2

wrcore_pkg.vhd modules/wrc_core/wrcore_pkg.vhd +16 -0

No files found.
--- a/modules/wrc_core/wr_core.vhd
+++ b/modules/wrc_core/wr_core.vhd
@@ -500,7 +500,7 @@ begin
    generic map(
      g_interface_mode       => PIPELINED,
      g_address_granularity  => BYTE,
-      g_ref_clock_rate       => 125000000,
+      g_ref_clock_rate       => f_refclk_rate(g_pcs_16bit),
      g_ext_clock_rate       => 10000000,
      g_with_ext_clock_input => g_with_external_clock_input)
    port map(
@@ -540,7 +540,7 @@ begin
      g_address_granularity  => BYTE,
      g_num_ref_inputs       => 1,
      g_num_outputs          => 1 + g_aux_clks,
-      g_ref_clock_rate       => 125000000,
+      g_ref_clock_rate       => f_refclk_rate(g_pcs_16bit),
      g_ext_clock_rate       => 10000000)
    port map(
      clk_sys_i => clk_sys_i,

--- a/modules/wrc_core/wrcore_pkg.vhd
+++ b/modules/wrc_core/wrcore_pkg.vhd
@@ -11,6 +11,8 @@ use work.softpll_pkg.all;

 package wrcore_pkg is

+  function f_refclk_rate(pcs_16 : boolean) return integer;
+
  ----------------------------------------------------------------------------- 
  --PPS generator
  -----------------------------------------------------------------------------
@@ -631,3 +633,17 @@ package wrcore_pkg is
  end component;

 end wrcore_pkg;
+
+package body wrcore_pkg is
+
+  function f_refclk_rate(pcs_16 : boolean)
+    return integer is
+  begin
+    if (pcs_16) then
+      return 62500000;
+    else
+      return 125000000;
+    end if;
+  end function;
+
+end package body wrcore_pkg;