Commit 09015310 authored by Grzegorz Daniluk's avatar Grzegorz Daniluk

platform/xilinx: adding detailed loopback vector to GTP

parent 9c2890c0
......@@ -109,6 +109,7 @@ entity wr_gtp_phy_spartan6 is
-- local loopback enable (Tx->Rx), active hi
ch0_loopen_i : in std_logic;
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
-- gtp0 ready: locked & aligned
ch0_rdy_o : out std_logic;
......@@ -129,6 +130,7 @@ entity wr_gtp_phy_spartan6 is
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch1_rdy_o : out std_logic;
-- Serial I/O
......@@ -393,6 +395,9 @@ begin -- rtl
ch0_rx_rec_clk_pad <= ch0_gtp_clkout_int(1);
ch0_ref_clk_in(0) <= gtp_clk_i;
ch0_ref_clk_in(1) <= '0';
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch0_gtp_loopback <= "010" when(ch0_loopen_i = '1') else
ch0_loopen_vec_i;
gen_disp_ch0 : process(ch0_ref_clk_i)
begin
......@@ -551,6 +556,9 @@ begin -- rtl
ch1_rx_rec_clk_pad <= ch1_gtp_clkout_int(1);
ch1_ref_clk_in(0) <= gtp_clk_i;
ch1_ref_clk_in(1) <= '0';
-- Near-end PMA loopback or loopback selected with ch1_loopen_vec_i
ch1_gtp_loopback <= "010" when(ch1_loopen_i = '1') else
ch1_loopen_vec_i;
gen_disp_ch1 : process(ch1_ref_clk_i)
begin
......
......@@ -28,6 +28,7 @@ package wr_xilinx_pkg is
ch0_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch0_rst_i : in std_logic := '0';
ch0_loopen_i : in std_logic := '0';
ch0_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch0_rdy_o : out std_logic;
ch1_ref_clk_i : in std_logic;
ch1_tx_data_i : in std_logic_vector(7 downto 0) := "00000000";
......@@ -41,6 +42,7 @@ package wr_xilinx_pkg is
ch1_rx_bitslide_o : out std_logic_vector(3 downto 0);
ch1_rst_i : in std_logic := '0';
ch1_loopen_i : in std_logic := '0';
ch1_loopen_vec_i : in std_logic_vector(2 downto 0) := (others=>'0');
ch1_rdy_o : out std_logic;
pad_txn0_o : out std_logic;
pad_txp0_o : out std_logic;
......
......@@ -360,6 +360,7 @@ architecture rtl of spec_top is
signal phy_rx_bitslide : std_logic_vector(3 downto 0);
signal phy_rst : std_logic;
signal phy_loopen : std_logic;
signal phy_loopen_vec : std_logic_vector(2 downto 0);
signal phy_rdy : std_logic;
signal dio_in : std_logic_vector(4 downto 0);
......@@ -697,6 +698,7 @@ begin
phy_rx_bitslide_i => phy_rx_bitslide,
phy_rst_o => phy_rst,
phy_loopen_o => phy_loopen,
phy_loopen_vec_o => phy_loopen_vec,
phy_rdy_i => phy_rdy,
led_act_o => LED_RED,
......@@ -817,6 +819,7 @@ begin
ch1_rx_bitslide_o => phy_rx_bitslide,
ch1_rst_i => phy_rst,
ch1_loopen_i => phy_loopen,
ch1_loopen_vec_i => phy_loopen_vec,
ch1_rdy_o => phy_rdy,
pad_txn0_o => open,
pad_txp0_o => open,
......
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