when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the…

when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the U_TX_FIFO to empty in order to catch the proper timestamp for the oob signalled packet.

when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the…
when oob.valid, ep_tx_pcs_16bit should (just as ep_tx_psc_8bit) wait for the U_TX_FIFO to empty in order to catch the proper timestamp for the oob signalled packet.
0e2172f0 · Peter Jansweijer · Grzegorz Daniluk · 196934e8 · 0e2172f0
Commit 0e2172f0 authored Mar 19, 2015 by Peter Jansweijer Committed by Grzegorz Daniluk Sep 01, 2015
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ep_tx_pcs_16bit.vhd modules/wr_endpoint/ep_tx_pcs_16bit.vhd +8 -11

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--- a/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
+++ b/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
@@ -520,22 +520,19 @@ begin
    end if;
  end process;

-  gen_tx_busy : process(tx_state)
+  process(phy_tx_clk_i)
  begin
-    case (tx_state) is
-      when TX_CR12 =>
-        tx_busy <= '0';
-      when TX_CR34 =>
-        tx_busy <= '0';
-      when TX_COMMA_IDLE =>
-        tx_busy <= '0';
-      when others =>
+    if rising_edge(phy_tx_clk_i) then
+      if fifo_empty = '0' or (tx_state /= TX_CR12 and tx_state /= TX_CR34 and tx_state /= TX_COMMA_IDLE) then
        tx_busy <= '1';
-    end case;
+      else
+        tx_busy <= '0';
+      end if;
+    end if;
  end process;

--  tx_busy    <= '1' when (fifo_empty = '0') or (tx_state /= TX_COMMA_IDLE) else '0';
  pcs_dreq_o <= not fifo_almost_full;
+  
 end behavioral;