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White Rabbit core collection
Commit c4fed35e authored by Grzegorz Daniluk's avatar Grzegorz Daniluk
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modules/endpoint: adding MDIO ECTRL register 

Register stores new fields that were added to MCR since MDIO regs can be only
16-bits.
parent d7afa48e
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Showing with 161 additions and 119 deletions
modules/wr_endpoint/endpoint_private_pkg.vhd
View file @ c4fed35e
......@@ -324,11 +324,6 @@ package endpoint_private_pkg is
mdio_mcr_anenable_o : out std_logic;
mdio_mcr_reset_o : out std_logic;
mdio_mcr_loopback_o : out std_logic;
mdio_mcr_lpbck_vec_o : out std_logic_vector(2 downto 0);
mdio_mcr_sfp_tx_fault_i : in std_logic;
mdio_mcr_sfp_loss_i : in std_logic;
mdio_mcr_sfp_tx_disable_o : out std_logic;
mdio_mcr_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
mdio_msr_lstatus_i : in std_logic;
lstat_read_notify_o : out std_logic;
mdio_msr_rfault_i : in std_logic;
......@@ -344,7 +339,12 @@ package endpoint_private_pkg is
mdio_wr_spec_tx_cal_o : out std_logic;
mdio_wr_spec_rx_cal_stat_i : in std_logic;
mdio_wr_spec_cal_crst_o : out std_logic;
mdio_wr_spec_bslide_i : in std_logic_vector(4 downto 0));
mdio_wr_spec_bslide_i : in std_logic_vector(4 downto 0);
mdio_ectrl_lpbck_vec_o : out std_logic_vector(2 downto 0);
mdio_ectrl_sfp_tx_fault_i : in std_logic;
mdio_ectrl_sfp_loss_i : in std_logic;
mdio_ectrl_sfp_tx_disable_o : out std_logic;
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0));
end component;
component ep_tx_header_processor
......
modules/wr_endpoint/ep_1000basex_pcs.vhd
View file @ c4fed35e
......@@ -437,11 +437,6 @@ begin -- rtl
mdio_mcr_anenable_o => mdio_mcr_anenable,
mdio_mcr_reset_o => mdio_mcr_reset,
mdio_mcr_loopback_o => serdes_loopen_o,
mdio_mcr_lpbck_vec_o => serdes_loopen_vec_o,
mdio_mcr_sfp_tx_fault_i => serdes_sfp_tx_fault_i,
mdio_mcr_sfp_loss_i => serdes_sfp_los_i,
mdio_mcr_sfp_tx_disable_o => serdes_sfp_tx_disable_o,
mdio_mcr_tx_prbs_sel_o => serdes_tx_prbs_sel_o,
mdio_msr_lstatus_i => mdio_msr_lstatus,
mdio_msr_rfault_i => mdio_msr_rfault,
mdio_msr_anegcomplete_i => mdio_msr_anegcomplete,
......@@ -457,6 +452,11 @@ begin -- rtl
mdio_wr_spec_rx_cal_stat_i => mdio_wr_spec_rx_cal_stat,
mdio_wr_spec_cal_crst_o => mdio_wr_spec_cal_crst,
mdio_wr_spec_bslide_i => mdio_wr_spec_bslide,
mdio_ectrl_lpbck_vec_o => serdes_loopen_vec_o,
mdio_ectrl_sfp_tx_fault_i => serdes_sfp_tx_fault_i,
mdio_ectrl_sfp_loss_i => serdes_sfp_los_i,
mdio_ectrl_sfp_tx_disable_o => serdes_sfp_tx_disable_o,
mdio_ectrl_tx_prbs_sel_o => serdes_tx_prbs_sel_o,
lstat_read_notify_o => lstat_read_notify
);
......
modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
View file @ c4fed35e
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ep_pcs_tbi_mdio_wb.vhd
-- Author : auto-generated by wbgen2 from pcs_regs.wb
-- Created : Tue Aug 4 12:12:43 2015
-- Created : Thu Aug 6 09:50:34 2015
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pcs_regs.wb
......@@ -41,16 +41,6 @@ entity ep_pcs_tbi_mdio_wb is
mdio_mcr_loopback_o : out std_logic;
-- Port for MONOSTABLE field: 'Reset' in reg: 'MDIO Control Register'
mdio_mcr_reset_o : out std_logic;
-- Port for std_logic_vector field: 'Loopback - detailed' in reg: 'MDIO Control Register'
mdio_mcr_lpbck_vec_o : out std_logic_vector(2 downto 0);
-- Port for BIT field: 'SFP TX Fault Status' in reg: 'MDIO Control Register'
mdio_mcr_sfp_tx_fault_i : in std_logic;
-- Port for BIT field: 'SFP LOS' in reg: 'MDIO Control Register'
mdio_mcr_sfp_loss_i : in std_logic;
-- Port for BIT field: 'SFP TX Disable' in reg: 'MDIO Control Register'
mdio_mcr_sfp_tx_disable_o : out std_logic;
-- Port for std_logic_vector field: 'tx_prbs_sel' in reg: 'MDIO Control Register'
mdio_mcr_tx_prbs_sel_o : out std_logic_vector(2 downto 0);
-- Port for BIT field: 'Link Status' in reg: 'MDIO Status Register'
mdio_msr_lstatus_i : in std_logic;
lstat_read_notify_o : out std_logic;
......@@ -81,7 +71,17 @@ entity ep_pcs_tbi_mdio_wb is
-- Port for asynchronous (clock: rx_clk_i) MONOSTABLE field: 'Reset calibration counter' in reg: 'WhiteRabbit-specific Configuration Register'
mdio_wr_spec_cal_crst_o : out std_logic;
-- Port for asynchronous (clock: rx_clk_i) std_logic_vector field: 'GTP RX Bitslide' in reg: 'WhiteRabbit-specific Configuration Register'
mdio_wr_spec_bslide_i : in std_logic_vector(4 downto 0)
mdio_wr_spec_bslide_i : in std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Loopback - detailed' in reg: 'MDIO Extended Control Register'
mdio_ectrl_lpbck_vec_o : out std_logic_vector(2 downto 0);
-- Port for BIT field: 'SFP TX Fault Status' in reg: 'MDIO Extended Control Register'
mdio_ectrl_sfp_tx_fault_i : in std_logic;
-- Port for BIT field: 'SFP LOS' in reg: 'MDIO Extended Control Register'
mdio_ectrl_sfp_loss_i : in std_logic;
-- Port for BIT field: 'SFP TX Disable' in reg: 'MDIO Extended Control Register'
mdio_ectrl_sfp_tx_disable_o : out std_logic;
-- Port for std_logic_vector field: 'tx_prbs_sel' in reg: 'MDIO Extended Control Register'
mdio_ectrl_tx_prbs_sel_o : out std_logic_vector(2 downto 0)
);
end ep_pcs_tbi_mdio_wb;
......@@ -95,9 +95,6 @@ signal mdio_mcr_anenable_int : std_logic ;
signal mdio_mcr_loopback_int : std_logic ;
signal mdio_mcr_reset_dly0 : std_logic ;
signal mdio_mcr_reset_int : std_logic ;
signal mdio_mcr_lpbck_vec_int : std_logic_vector(2 downto 0);
signal mdio_mcr_sfp_tx_disable_int : std_logic ;
signal mdio_mcr_tx_prbs_sel_int : std_logic_vector(2 downto 0);
signal mdio_advertise_pause_int : std_logic_vector(1 downto 0);
signal mdio_advertise_rfault_int : std_logic_vector(1 downto 0);
signal mdio_wr_spec_tx_cal_int : std_logic ;
......@@ -117,6 +114,9 @@ signal mdio_wr_spec_bslide_lwb_in_progress : std_logic ;
signal mdio_wr_spec_bslide_lwb_s0 : std_logic ;
signal mdio_wr_spec_bslide_lwb_s1 : std_logic ;
signal mdio_wr_spec_bslide_lwb_s2 : std_logic ;
signal mdio_ectrl_lpbck_vec_int : std_logic_vector(2 downto 0);
signal mdio_ectrl_sfp_tx_disable_int : std_logic ;
signal mdio_ectrl_tx_prbs_sel_int : std_logic_vector(2 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
......@@ -150,9 +150,6 @@ begin
mdio_mcr_anenable_int <= '0';
mdio_mcr_loopback_int <= '0';
mdio_mcr_reset_int <= '0';
mdio_mcr_lpbck_vec_int <= "000";
mdio_mcr_sfp_tx_disable_int <= '0';
mdio_mcr_tx_prbs_sel_int <= "000";
lstat_read_notify_o <= '0';
mdio_advertise_pause_int <= "00";
mdio_advertise_rfault_int <= "00";
......@@ -162,6 +159,9 @@ begin
mdio_wr_spec_bslide_lwb <= '0';
mdio_wr_spec_bslide_lwb_delay <= '0';
mdio_wr_spec_bslide_lwb_in_progress <= '0';
mdio_ectrl_lpbck_vec_int <= "000";
mdio_ectrl_sfp_tx_disable_int <= '0';
mdio_ectrl_tx_prbs_sel_int <= "000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
......@@ -193,9 +193,6 @@ begin
mdio_mcr_anenable_int <= wrdata_reg(12);
mdio_mcr_loopback_int <= wrdata_reg(14);
mdio_mcr_reset_int <= wrdata_reg(15);
mdio_mcr_lpbck_vec_int <= wrdata_reg(18 downto 16);
mdio_mcr_sfp_tx_disable_int <= wrdata_reg(21);
mdio_mcr_tx_prbs_sel_int <= wrdata_reg(24 downto 22);
end if;
rddata_reg(4 downto 0) <= "00000";
rddata_reg(5) <= mdio_mcr_uni_en_int;
......@@ -209,11 +206,15 @@ begin
rddata_reg(13) <= '0';
rddata_reg(14) <= mdio_mcr_loopback_int;
rddata_reg(15) <= '0';
rddata_reg(18 downto 16) <= mdio_mcr_lpbck_vec_int;
rddata_reg(19) <= mdio_mcr_sfp_tx_fault_i;
rddata_reg(20) <= mdio_mcr_sfp_loss_i;
rddata_reg(21) <= mdio_mcr_sfp_tx_disable_int;
rddata_reg(24 downto 22) <= mdio_mcr_tx_prbs_sel_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
......@@ -458,6 +459,42 @@ begin
rddata_reg(31) <= 'X';
ack_sreg(5) <= '1';
ack_in_progress <= '1';
when "10001" =>
if (wb_we_i = '1') then
mdio_ectrl_lpbck_vec_int <= wrdata_reg(2 downto 0);
mdio_ectrl_sfp_tx_disable_int <= wrdata_reg(5);
mdio_ectrl_tx_prbs_sel_int <= wrdata_reg(10 downto 8);
end if;
rddata_reg(2 downto 0) <= mdio_ectrl_lpbck_vec_int;
rddata_reg(3) <= mdio_ectrl_sfp_tx_fault_i;
rddata_reg(4) <= mdio_ectrl_sfp_loss_i;
rddata_reg(5) <= mdio_ectrl_sfp_tx_disable_int;
rddata_reg(10 downto 8) <= mdio_ectrl_tx_prbs_sel_int;
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
......@@ -505,14 +542,6 @@ begin
end process;
-- Loopback - detailed
mdio_mcr_lpbck_vec_o <= mdio_mcr_lpbck_vec_int;
-- SFP TX Fault Status
-- SFP LOS
-- SFP TX Disable
mdio_mcr_sfp_tx_disable_o <= mdio_mcr_sfp_tx_disable_int;
-- tx_prbs_sel
mdio_mcr_tx_prbs_sel_o <= mdio_mcr_tx_prbs_sel_int;
-- Link Status
-- Remote Fault
-- Auto-Negotiation Complete
......@@ -593,6 +622,14 @@ begin
end process;
-- Loopback - detailed
mdio_ectrl_lpbck_vec_o <= mdio_ectrl_lpbck_vec_int;
-- SFP TX Fault Status
-- SFP LOS
-- SFP TX Disable
mdio_ectrl_sfp_tx_disable_o <= mdio_ectrl_sfp_tx_disable_int;
-- tx_prbs_sel
mdio_ectrl_tx_prbs_sel_o <= mdio_ectrl_tx_prbs_sel_int;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
......
modules/wr_endpoint/pcs_regs.wb
View file @ c4fed35e
......@@ -174,70 +174,6 @@ peripheral {
prefix = "reset";
type = MONOSTABLE;
};
field {
name = "Loopback - detailed";
description = "Loopback vector for Xilinx PHYs: \
100 = far end loopback mode \
000 = normal mode \
See also Transceiver documentation (for example Xilinx UG476 Table 2-37 and Figure 2-23 \
LOOPBACK bit set to 1 may overwritte LPBCK_VEC depending on the PHY wrapper implementation";
prefix = "lpbck_vec";
align = 16;
size = 3;
value = 0;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SFP TX Fault Status";
description = "1 = Some kind of laser failure\
0 = SFP Laser okay";
prefix = "sfp_tx_fault";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "SFP LOS";
description = "1 = Loss of signal\
0 = SFP Receiver signal strength okay";
prefix = "sfp_loss";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "SFP TX Disable";
description = "Disables the SFP Transmitter \
1 = SFP TX Disabled\
0 = SFP TX Enabled";
prefix = "sfp_tx_disable";
type = BIT;
value = 0;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx_prbs_sel";
description = "PRBS selection \
000 = Normal mode\
0010 = PRBS-7";
prefix = "tx_prbs_sel";
align = 22;
size = 3;
value = 0;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
......@@ -784,5 +720,73 @@ peripheral {
clock = "rx_clk_i";
};
};
reg {
name = "MDIO Extended Control Register";
prefix = "ECTRL";
field {
name = "Loopback - detailed";
description = "Loopback vector for Xilinx PHYs: \
100 = far end loopback mode \
000 = normal mode \
See also Transceiver documentation (for example Xilinx UG476 Table 2-37 and Figure 2-23 \
LOOPBACK bit set to 1 in MCR register may override LPBCK_VEC depending on the PHY wrapper implementation";
prefix = "lpbck_vec";
align = 0;
size = 3;
value = 0;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "SFP TX Fault Status";
description = "1 = Some kind of laser failure\
0 = SFP Laser okay";
prefix = "sfp_tx_fault";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "SFP LOS";
description = "1 = Loss of signal\
0 = SFP Receiver signal strength okay";
prefix = "sfp_loss";
type = BIT;
access_bus=READ_ONLY;
access_dev=WRITE_ONLY;
};
field {
name = "SFP TX Disable";
description = "Disables the SFP Transmitter \
1 = SFP TX Disabled\
0 = SFP TX Enabled";
prefix = "sfp_tx_disable";
type = BIT;
value = 0;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "tx_prbs_sel";
description = "PRBS selection \
000 = Normal mode\
0010 = PRBS-7";
prefix = "tx_prbs_sel";
align = 8;
size = 3;
value = 0;
type = SLV;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
sim/endpoint_mdio.v
View file @ c4fed35e
......@@ -23,16 +23,6 @@
`define MDIO_MCR_LOOPBACK 32'h00004000
`define MDIO_MCR_RESET_OFFSET 15
`define MDIO_MCR_RESET 32'h00008000
`define MDIO_MCR_LPBCK_VEC_OFFSET 16
`define MDIO_MCR_LPBCK_VEC 32'h00070000
`define MDIO_MCR_SFP_TX_FAULT_OFFSET 19
`define MDIO_MCR_SFP_TX_FAULT 32'h00080000
`define MDIO_MCR_SFP_LOSS_OFFSET 20
`define MDIO_MCR_SFP_LOSS 32'h00100000
`define MDIO_MCR_SFP_TX_DISABLE_OFFSET 21
`define MDIO_MCR_SFP_TX_DISABLE 32'h00200000
`define MDIO_MCR_TX_PRBS_SEL_OFFSET 22
`define MDIO_MCR_TX_PRBS_SEL 32'h01c00000
`define ADDR_MDIO_MSR 7'h4
`define MDIO_MSR_ERCAP_OFFSET 0
`define MDIO_MSR_ERCAP 32'h00000001
......@@ -139,3 +129,14 @@
`define MDIO_WR_SPEC_CAL_CRST 32'h00000004
`define MDIO_WR_SPEC_BSLIDE_OFFSET 4
`define MDIO_WR_SPEC_BSLIDE 32'h000001f0
`define ADDR_MDIO_ECTRL 7'h44
`define MDIO_ECTRL_LPBCK_VEC_OFFSET 0
`define MDIO_ECTRL_LPBCK_VEC 32'h00000007
`define MDIO_ECTRL_SFP_TX_FAULT_OFFSET 3
`define MDIO_ECTRL_SFP_TX_FAULT 32'h00000008
`define MDIO_ECTRL_SFP_LOSS_OFFSET 4
`define MDIO_ECTRL_SFP_LOSS 32'h00000010
`define MDIO_ECTRL_SFP_TX_DISABLE_OFFSET 5
`define MDIO_ECTRL_SFP_TX_DISABLE 32'h00000020
`define MDIO_ECTRL_TX_PRBS_SEL_OFFSET 8
`define MDIO_ECTRL_TX_PRBS_SEL 32'h00000700
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