Commits · 6f24e281bcf21c4bdeab1844442fc67671d11b38 · Projects / VME64x core

24 Jan, 2020 3 commits
- simple_tb: add one transaction. · 6f24e281
  Tristan Gingold authored Jan 24, 2020
  
  6f24e281
- vme_bus: precharge data. · d8458a00
  Tristan Gingold authored Jan 24, 2020
  
  d8458a00
- vme_bus: improve direction driving. · 5f8a8d76
  Tristan Gingold authored Jan 24, 2020
  
  5f8a8d76
23 Jan, 2020 5 commits
- vme_bus: cleanup · a3da2998
  Tristan Gingold authored Jan 23, 2020
  
  a3da2998
- vme_bus: cleanup · 4afbed6d
  Tristan Gingold authored Jan 23, 2020
  
  4afbed6d
- vme_bus: simulation is OK. · 2a6ec06b
  Tristan Gingold authored Jan 23, 2020
  
  2a6ec06b
- top_tb: add debug code. · 3ee97c19
  Tristan Gingold authored Jan 23, 2020
  
  3ee97c19
- vme_bus: new prefetch. · f41cbe6f
  Tristan Gingold authored Jan 23, 2020
  
  f41cbe6f
22 Jan, 2020 5 commits
- simple_tb: simulate propagation for dtack. · a20e1852
  Tristan Gingold authored Jan 22, 2020
  
  a20e1852
- vme_bus: renaming. · 2c24dd8d
  Tristan Gingold authored Jan 22, 2020
  
  2c24dd8d
- vme_bus: reformatting. · 4e2e39c2
  Tristan Gingold authored Jan 22, 2020
  
  4e2e39c2
- Add vme_bus.vhd original modifications from Milos Vojinovic. · 8ef0259b
  Tristan Gingold authored Jan 22, 2020
  
  8ef0259b
- Reference general-cores with a git module. · 436b5396
  Tristan Gingold authored Jan 22, 2020
  
  436b5396
14 Nov, 2019 1 commit
- Add a comment. · 6abee52c
  Tristan Gingold authored Nov 14, 2019
  
  6abee52c
11 Nov, 2019 5 commits
- Add vme16_tb testbench · 7b94b276
  Tristan Gingold authored Nov 11, 2019
  
  7b94b276
- Add ghdl support for simple_tb. · 2736fdff
  Tristan Gingold authored Nov 11, 2019
  
  2736fdff
- vme64x_pkg: rename c_AM_A24_S to c_AM_A24 · a994813b
  Tristan Gingold authored Nov 11, 2019
  
  a994813b
- vme64x_core: add g_VME32 generic (true by default). · b9f87fb9
  Tristan Gingold authored Nov 11, 2019
```
Add support for a D16 only (still with D8) core.
```
  b9f87fb9
- top_tb: add entity name after 'end' for the sake of hdlmake. · 84da9bdd
  Tristan Gingold authored Nov 11, 2019
  
  84da9bdd
24 Jul, 2019 3 commits
- simple_tb: adjust scenario 9. · 366ca4db
  Tristan Gingold authored Jul 24, 2019
  
  366ca4db
- sim: cleanup in vme bfm. · 3dd0b23a
  Tristan Gingold authored Jul 24, 2019
  
  3dd0b23a
- xvme64x_core: add g_WB_MODE generic to select between classic/pipelined. · 4d39f9df
  Tristan Gingold authored Jul 24, 2019
  
  4d39f9df
02 Apr, 2019 1 commit
- Update general-cores submodule URL for new OHWR · 1204aeca
  Tom Levens authored Apr 02, 2019
  
  1204aeca
29 Nov, 2018 1 commit
- Invert RTY assertion logic to make simulators happier · 78cac871
  Dimitris Lampridis authored Nov 23, 2018
  
  78cac871
26 Oct, 2018 4 commits
- Implement amnesia address if parity is wrong · e0f5eaad
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  e0f5eaad
- Add new generic to component declaration · ae052e76
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  ae052e76
- Cleanup alignment of code · c3d44ce4
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  c3d44ce4
- Fix references to ANSI/VITA standards · 45cb91f4
  Tom Levens authored Oct 26, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  45cb91f4
25 Oct, 2018 3 commits
- Add generic to disable CR/CSR · 44f9345f
  Tom Levens authored Oct 25, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  44f9345f
- Normalise case of generics and ports · a2ee4ac4
  Tom Levens authored Oct 25, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  a2ee4ac4
- Propagate defaults to parameters on vme64x_core · cd83b258
  Tom Levens authored Oct 25, 2018
```
Signed-off-by: Tom Levens <tom.levens@cern.ch>
```
  cd83b258
17 Aug, 2018 4 commits
- run_all.sh: strenghten. · 0ae24a25
  Tristan Gingold authored Aug 17, 2018
  
  0ae24a25
- vme_bus: wait for ack = 0 between MBLT WB xfer. · fd6dce67
  Tristan Gingold authored Aug 17, 2018
  
  fd6dce67
- MTLB: force stb to 1 after the first WB transaction. · c50928bb
  Tristan Gingold authored Aug 17, 2018
  
  c50928bb
- Wait until wb ack is negated before starting the second MBLT wb transaction. · c1ab84ba
  Tristan Gingold authored Aug 17, 2018
  
  c1ab84ba
21 Mar, 2018 1 commit
- hdl: bump general-cores used for simulations in order to bring in the WB int removal done there · 633d3174
  Dimitris Lampridis authored Mar 21, 2018
  
  633d3174
20 Mar, 2018 1 commit
- hdl: further cleanup of WB INT and default value for int input when not used · 73232ebd
  Dimitris Lampridis authored Mar 20, 2018
  
  73232ebd
09 Mar, 2018 1 commit
- Document inverted VME signal from V1 to V2. · a120e226
  Tristan Gingold authored Mar 09, 2018
  
  a120e226
08 Mar, 2018 1 commit
- Add missing separate interrupt input line to component declaration in vme64x package as well · 258f8f68
  Dimitris Lampridis authored Mar 08, 2018
  
  258f8f68
06 Mar, 2018 1 commit
- Use a separate pin for the interrupt input line. · 58d3d619
  Tristan Gingold authored Mar 06, 2018
  
  58d3d619