Skip to content

V
VME64x core
Commit 366ca4db authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

simple_tb: adjust scenario 9.

parent 3dd0b23a
Hide whitespace changes
Inline Side-by-side
Showing with 30 additions and 77 deletions
hdl/testbench/simple_tb/Manifest.py
View file @ 366ca4db
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"top_tb.vhd",
]
modules = {
"local": [ "../../rtl", "../../ip_cores/general-cores" ],
"local": [ "../../rtl", fetchto + "/general-cores" ],
}
hdl/testbench/simple_tb/modelsim/wave.do
View file @ 366ca4db
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/clk_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/rst_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_AS_n_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_LWORD_n_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_LWORD_n_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_RETRY_n_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_RETRY_OE_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_WRITE_n_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_DS_n_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_DTACK_n_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_DTACK_OE_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_BERR_n_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_ADDR_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_ADDR_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_ADDR_DIR_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_ADDR_OE_N_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_DATA_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_DATA_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_DATA_DIR_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_DATA_OE_N_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_AM_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_IACKIN_n_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_IACK_n_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/VME_IACKOUT_n_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/stb_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/ack_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/dat_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/dat_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/adr_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/sel_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/we_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/cyc_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/err_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/stall_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/addr_decoder_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/addr_decoder_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/decode_start_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/decode_done_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/am_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/decode_sel_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/cr_csr_addr_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/cr_csr_data_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/cr_csr_data_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/cr_csr_we_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/module_enable_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/bar_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/INT_Level_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/INT_Vector_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/irq_pending_i
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/irq_ack_o
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_locDataIn
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_locDataOut
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_ADDRlatched
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_LWORDlatched_n
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_DSlatched_n
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_AMlatched
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_WRITElatched_n
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_vme_addr_reg
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_vme_data_reg
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_vme_lword_n_reg
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_vme_addr_dir
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_addressingType
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_transferType
add wave -noupdate -height 16 /top_tb/vme64xcore/Inst_VME_bus/s_mainFSMstate
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_conf_req
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_dataPhase
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_MBLT_Data
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_conf_sel
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_card_sel
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_irq_sel
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_err
add wave -noupdate /top_tb/vme64xcore/Inst_VME_bus/s_DS_latch_count
add wave -noupdate /top_tb/vme64xcore/vme_am_i
add wave -noupdate /top_tb/vme64xcore/vme_ds_n_i
add wave -noupdate /top_tb/vme64xcore/vme_ga_i
add wave -noupdate /top_tb/vme64xcore/vme_data_i
add wave -noupdate /top_tb/vme64xcore/vme_addr_i
add wave -noupdate /top_tb/vme64xcore/vme_data_o
add wave -noupdate /top_tb/vme64xcore/vme_addr_o
add wave -noupdate /top_tb/vme64xcore/vme_irq_n_o
add wave -noupdate /top_tb/vme64xcore/wb_dat_i
add wave -noupdate /top_tb/vme64xcore/wb_adr_o
add wave -noupdate /top_tb/vme64xcore/wb_sel_o
add wave -noupdate /top_tb/vme64xcore/wb_dat_o
add wave -noupdate /top_tb/vme64xcore/irq_level_i
add wave -noupdate /top_tb/vme64xcore/irq_vector_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {5417751726 ps} 0}
WaveRestoreCursors {{Cursor 1} {782462 ps} 0}
quietly wave cursor active 1
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -88,4 +31,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {21356173874 ps}
WaveRestoreZoom {0 ps} {1301139 ps}
hdl/testbench/simple_tb/top_tb.vhd
View file @ 366ca4db
......@@ -1342,7 +1342,7 @@ begin
-- Try to read with a wrong AM.
read8 (x"56_00_00_00", c_AM_A32_SUP, d8);
if g_SCENARIO = 8 then
assert d8 = "XXXXXXXX" report "unexpected reply" severity error;
assert d8 = "XXXXXXXX" report "unexpected reply (a32sup)" severity error;
else
assert d8 = x"00"
report "bad read at 000 (no AM decode)" severity error;
......@@ -1350,7 +1350,12 @@ begin
-- However, the A24 decoder is not enabled.
read8 (x"56_00_00_00", c_AM_A24_S, d8);
assert d8 = "XXXXXXXX" report "unexpected reply" severity error;
if g_SCENARIO = 8 then
assert d8 = "XXXXXXXX" report "unexpected reply (a24s)" severity error;
else
assert d8 = x"00"
report "bad read at 000 (no AM decode)" severity error;
end if;
-- TODO: check IACK propagation.
end case;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment