Commit b9f87fb9 authored by Tristan Gingold's avatar Tristan Gingold

vme64x_core: add g_VME32 generic (true by default).

Add support for a D16 only (still with D8) core.
parent 84da9bdd
......@@ -15,6 +15,7 @@ entity vme64x_core is
g_DECODE_AM : boolean := true;
g_ENABLE_CR_CSR : boolean := true;
g_USER_CSR_EXT : boolean := false;
g_VME32 : boolean := true;
g_WB_GRANULARITY : t_wishbone_address_granularity;
g_MANUFACTURER_ID : std_logic_vector(23 downto 0);
g_BOARD_ID : std_logic_vector(31 downto 0);
......@@ -113,6 +114,7 @@ begin
g_DECODE_AM => g_DECODE_AM,
g_ENABLE_CR_CSR => g_ENABLE_CR_CSR,
g_USER_CSR_EXT => g_USER_CSR_EXT,
g_VME32 => g_VME32,
g_WB_GRANULARITY => g_WB_GRANULARITY,
g_WB_MODE => CLASSIC,
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
......
......@@ -33,7 +33,8 @@ use work.wishbone_pkg.all;
entity vme_bus is
generic (
g_CLOCK_PERIOD : integer;
g_CLOCK_PERIOD : integer;
g_VME32 : boolean;
g_WB_GRANULARITY : t_wishbone_address_granularity;
g_WB_MODE : t_wishbone_interface_mode
);
......@@ -367,6 +368,9 @@ begin
if s_LWORDlatched_n = '0' and s_ADDRlatched(1) = '1' then
-- unaligned.
s_mainFSMstate <= WAIT_END;
elsif g_VME32 = False and s_LWORDlatched_n = '0' then
-- No 32bit access on VME16.
s_mainFSMstate <= WAIT_END;
else
if s_ADDRlatched(23 downto 19) = bar_i
and s_AMlatched = c_AM_CR_CSR
......@@ -439,7 +443,7 @@ begin
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= '0';
if s_transferType = MBLT then
if g_VME32 and s_transferType = MBLT then
s_dataPhase <= '1';
-- Start with D[31..0] when writing, but D[63..32] when reading.
......@@ -477,7 +481,7 @@ begin
s_dataPhase <= s_dataPhase;
-- vme_addr is an output during MBLT *read* data transfer.
if s_transferType = MBLT and s_WRITElatched_n = '1' then
if s_transferType = MBLT and s_WRITElatched_n = '1' and g_VME32 then
s_vme_addr_dir <= '1';
else
s_vme_addr_dir <= '0';
......@@ -485,15 +489,21 @@ begin
s_locDataIn(32) <= s_LWORDlatched_n;
s_locDataIn(31 downto 0) <= s_vme_data_reg;
if s_vme_lword_n_reg = '1' and s_vme_addr_reg(1) = '0' then
if s_vme_lword_n_reg = '1' and s_vme_addr_reg(1) = '0' and g_VME32 then
-- Word/byte access with A1=0
s_locDataIn(31 downto 16) <= s_vme_data_reg(15 downto 0);
end if;
-- Translate DS+LWORD+ADDR to WB byte selects
if s_vme_lword_n_reg = '0' then
if not g_VME32 then
-- 16bit access on a 16bit bus.
wb_sel_o (3 downto 2) <= "00";
wb_sel_o (1 downto 0) <= not s_DSlatched_n;
elsif s_vme_lword_n_reg = '0' then
-- 32bit access
wb_sel_o <= "1111";
else
-- 16bit access on a 32bit bus.
wb_sel_o <= "0000";
case s_vme_addr_reg(1) is
when '0' =>
......@@ -504,7 +514,7 @@ begin
null;
end case;
end if;
-- ANSI/VITA 1-1994 Rule 2.6
-- A Slave MUST NOT respond with a falling edge on DTACK* during
-- an unaligned transfer cycle, if it does not have UAT
......@@ -571,8 +581,8 @@ begin
s_locDataOut(63 downto 32) <= s_locDataOut(31 downto 0);
s_locDataOut(31 downto 0) <= (others => '0');
if s_card_sel = '1' then
if s_vme_lword_n_reg = '1' and s_vme_addr_reg(1) = '0' then
-- Word/byte access with A1 = 0
if g_VME32 and s_vme_lword_n_reg = '1' and s_vme_addr_reg(1) = '0' then
-- Word/byte access with A1 = 0 on a 32bit bus.
s_locDataOut(15 downto 0) <= wb_dat_i(31 downto 16);
else
s_locDataOut(31 downto 0) <= wb_dat_i;
......@@ -581,7 +591,7 @@ begin
s_locDataOut(7 downto 0) <= cr_csr_data_i;
end if;
if s_dataPhase = '1' then
if s_dataPhase = '1' and g_VME32 then
-- MBLT
s_dataPhase <= '0';
s_vme_addr_reg(2) <= '1';
......@@ -614,8 +624,11 @@ begin
vme_data_dir_o <= s_WRITElatched_n;
vme_addr_dir_o <= s_vme_addr_dir;
vme_addr_o <= s_locDataOut(63 downto 33);
vme_lword_n_o <= s_locDataOut(32);
if g_VME32 then
-- only for MBLT
vme_addr_o <= s_locDataOut(63 downto 33);
vme_lword_n_o <= s_locDataOut(32);
end if;
vme_data_o <= s_locDataOut(31 downto 0);
-- ANSI/VITA 1-1994 Rule 2.54a
......@@ -656,7 +669,7 @@ begin
-- the same address (RMW).
s_mainFSMstate <= WAIT_FOR_DS;
else
if s_transferType = MBLT and s_MBLT_Data = '0' then
if g_VME32 and s_transferType = MBLT and s_MBLT_Data = '0' then
-- MBLT: end of address phase.
s_mainFSMstate <= WAIT_FOR_DS;
s_MBLT_Data <= '1';
......@@ -673,7 +686,7 @@ begin
vme_dtack_oe_o <= '1';
vme_addr_dir_o <= s_vme_addr_dir;
if s_vme_lword_n_reg = '0' then
if g_VME32 and s_vme_lword_n_reg = '0' then
if s_transferType = MBLT then
-- 64 bit
addr_word_incr := 4;
......@@ -740,9 +753,16 @@ begin
vme_retry_oe_o <= '0';
-- WB Master
with g_WB_GRANULARITY select
wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2) when WORD,
s_vme_addr_reg(31 downto 2) & "00" when BYTE;
g_wb_addr32: if g_VME32 generate
with g_WB_GRANULARITY select
wb_adr_o <= "00" & s_vme_addr_reg(31 downto 2) when WORD,
s_vme_addr_reg(31 downto 2) & "00" when BYTE;
end generate;
g_wb_addr16: if not g_VME32 generate
with g_WB_GRANULARITY select
wb_adr_o <= "0" & s_vme_addr_reg(31 downto 1) when WORD,
s_vme_addr_reg(31 downto 1) & "0" when BYTE;
end generate;
wb_we_o <= not s_WRITElatched_n;
wb_dat_o <= s_locDataIn(31 downto 0);
......
......@@ -36,6 +36,7 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
......@@ -56,6 +57,11 @@ entity xvme64x_core is
-- Use external user CSR
g_USER_CSR_EXT : boolean := false;
-- If False, handle 16bit backplane, ie not support for P1.
-- Capbilities are reduced: no A32, no D32, no MBLT.
-- As a consequence, it uses a 16bit data wishbone bus.
g_VME32 : boolean := True;
-- Address granularity on the WB bus. Value can be:
-- WORD: VME address bits 31:2 are translated to WB address bits 29:0,
-- the WB data represents bytes for VME address bits 1:0.
......@@ -177,7 +183,7 @@ architecture rtl of xvme64x_core is
function compute_static_ader (ga : std_logic_vector(4 downto 0)) return t_ader_array is
variable a : t_ader_array(0 to c_last_ader) := (others => x"0000_0000");
begin
for i in 0 to a'length-1 loop
for i in a'range loop
if g_DECODER(i).adem /= x"0000_0000" then
a(i) := std_logic_vector(resize(unsigned(ga), 32) sll least_set_bit(g_DECODER(i).adem));
end if;
......@@ -230,7 +236,7 @@ architecture rtl of xvme64x_core is
constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) :=
(16#38# to 16#3f# => '1', -- A24
16#2d# | 16#29# => '1', -- A16
16#08# to 16#0f# => '1', -- A32
16#08# to 16#0f# => f_to_std_logic(g_VME32), -- A32
others => '0');
begin
assert g_CLOCK_PERIOD > 0 report "g_CLOCK_PERIOD generic must be set"
......@@ -312,6 +318,7 @@ begin
inst_vme_bus : entity work.vme_bus
generic map (
g_CLOCK_PERIOD => g_CLOCK_PERIOD,
g_VME32 => g_VME32,
g_WB_GRANULARITY => g_WB_GRANULARITY,
g_WB_MODE => g_WB_MODE)
port map (
......@@ -434,6 +441,8 @@ begin
-- CR/CSR space
------------------------------------------------------------------------------
gen_enable_cr_csr : if g_ENABLE_CR_CSR = true generate
assert g_VME32 report "CS/CSR requires VME32 (uses a 32bit bus)" severity failure;
inst_vme_cr_csr_space : entity work.vme_cr_csr_space
generic map (
g_MANUFACTURER_ID => g_MANUFACTURER_ID,
......
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