Commits · 85f8c39cc1f845423b3566e57a956ccb502ca2e0 · Projects / Hdlmake · Open Hardware Repository

09 Apr, 2020 2 commits
- Organize HDL file extensions in sets and use them in the CXF parser · 85f8c39c
  Christos Gentsos authored Apr 09, 2020
  
  85f8c39c
- Implement Microsemi IP Core parsing; finds cxf deps w/o a manifest · 80e7a57b
  Christos Gentsos authored Apr 09, 2020
  
  80e7a57b
08 Apr, 2020 4 commits
- Override MAKEFILE_SYN_BUILD_CMD in LiberoSoc for TCL_INTERPRETER spc · b961c9b8
  Christos Gentsos authored Apr 08, 2020
  
  b961c9b8
- Partial revert of patch and baselines for TCL_INTERPRETER. · f8bec992
  Tristan Gingold authored Apr 08, 2020
```
For most tools, the space is needed.
```
  f8bec992
- Set top before enabling constraints in LiberoSoc, otherwise it fails · c0768c21
  Christos Gentsos authored Apr 08, 2020
  
  c0768c21
- Fix HDL source list generation for LiberoSoc synthesis target · e002c31e
  Christos Gentsos authored Apr 08, 2020
  
  e002c31e
07 Apr, 2020 2 commits
- Update reference Makefiles in testsuite for changes due to b2df73e8 · 734494db
  Christos Gentsos authored Apr 07, 2020
  
  734494db
- Merge branch 'origin/shaas-liberosoc-support' into develop · a3abe700
  Christos Gentsos authored Apr 07, 2020
  
  a3abe700
06 Apr, 2020 2 commits
- Produce a warning when an included Makefile cannot be found · 49b0ba49
  Christos Gentsos authored Apr 06, 2020
  
  49b0ba49
- Add test for context handling (added in commit cbc99517 ) · e6ab358e
  Christos Gentsos authored Apr 06, 2020
  
  e6ab358e
30 Mar, 2020 2 commits
- Add test for previous commit. · c0522d30
  Tristan Gingold authored Mar 30, 2020
  
  c0522d30
- vhdl_parser: ignore 'use work.all' · d6694bf2
  Tristan Gingold authored Mar 30, 2020
  
  d6694bf2
16 Mar, 2020 1 commit
- xilinx.py: add all source files at once. Update baselines. · c0a0320a
  Tristan Gingold authored Mar 16, 2020
  
  c0a0320a
12 Mar, 2020 3 commits
- ghdl_syn.py: add options, refactoring, add vhdl system library. · 4d6eef48
  Tristan Gingold authored Mar 12, 2020
  
  4d6eef48
- systemlibs.py: add 'vhdl' system library. · 3b861b35
  Tristan Gingold authored Mar 12, 2020
  
  3b861b35
- new_dep_solver: improve error message for unknown system library. · e107f68a
  Tristan Gingold authored Mar 12, 2020
  
  e107f68a
06 Mar, 2020 2 commits
- vlog_parser: improve speed of _filter_protected_regions. · 558bec34
  Tristan Gingold authored Mar 06, 2020
  
  558bec34
- vivado: clean the .sim project. · 9b8cf16c
  Tristan Gingold authored Mar 06, 2020
```
From J.R.Gill
```
  9b8cf16c
05 Mar, 2020 13 commits
- vhdl_parser: handle context declarations and specifications · cbc99517
  Christos Gentsos authored Mar 05, 2020
  
  cbc99517
- Add more modules for xilinx system lib. · eb09e8ec
  Tristan Gingold authored Mar 05, 2020
  
  eb09e8ec
- Clean libraries for ghdl. · 2366d4f2
  Tristan Gingold authored Mar 05, 2020
  
  2366d4f2
- testsuite: improve test 027vhdl_parser · c227a82a
  Tristan Gingold authored Mar 05, 2020
  
  c227a82a
- vhdl_parser: handle component instantiations. · a7abea45
  Tristan Gingold authored Mar 05, 2020
```
with 'component' reserved identifier.  Tune the direct
instantiation pattern.

From nico
```
  a7abea45
- vhdl_parser: adjust regexp · 8a945172
  Tristan Gingold authored Mar 05, 2020
  
  8a945172
- hdlmake: add command --list-deps · 0b6ba299
  Tristan Gingold authored Mar 05, 2020
  
  0b6ba299
- action.py: minor renaming. · b27ba540
  Tristan Gingold authored Mar 05, 2020
  
  b27ba540
- vhdl_parser: minor refactoring of instance_pattern. · 8682c7ba
  Tristan Gingold authored Mar 05, 2020
  
  8682c7ba
- vhdl_parser: remove unused variable. · 7429cb98
  Tristan Gingold authored Mar 05, 2020
  
  7429cb98
- Support library for xci files. · 9c3a2375
  Tristan Gingold authored Mar 05, 2020
```
From nico.
```
  9c3a2375
- xilinx tools: set library on source files. · 4e09765b
  Tristan Gingold authored Mar 05, 2020
```
From nico
```
  4e09765b
- Add the notion of system libraries. · a29e6a9f
  Tristan Gingold authored Mar 05, 2020
```
Avoid reports of not satisfied relations for system libraries and modules.
```
  a29e6a9f
04 Mar, 2020 6 commits
- Add 'system' modules (currently only xilinx). · d3cb6f5b
  Tristan Gingold authored Mar 04, 2020
  
  d3cb6f5b
- Minor renaming. Add comments. · 417d1f93
  Tristan Gingold authored Mar 04, 2020
  
  417d1f93
- optimization: do not reparse modules already loaded. · 82d2f907
  Tristan Gingold authored Mar 04, 2020
  
  82d2f907
- module.py: minor rewrite, add comments. · b20754ab
  Tristan Gingold authored Mar 04, 2020
  
  b20754ab
- Minor renaming, comments added. · 49355279
  Tristan Gingold authored Mar 04, 2020
  
  49355279
- vhdl_parser: handle entities without name after 'end'. · 614874ec
  Tristan Gingold authored Mar 04, 2020
  
  614874ec
02 Mar, 2020 2 commits
- Add a test for previous commit. · 11ebf1d0
  Tristan Gingold authored Mar 02, 2020
  
  11ebf1d0
- vlog_parser: handles empty module/interface. · c8be2839
  Tristan Gingold authored Mar 02, 2020
  
  c8be2839
26 Feb, 2020 1 commit
- makefilevsim: rework stamp files. · 5495d573
  Tristan Gingold authored Feb 26, 2020
```
This avoid mkdir errors on windows.
```
  5495d573