Commit c227a82a authored by Tristan Gingold's avatar Tristan Gingold

testsuite: improve test 027vhdl_parser

parent a7abea45
......@@ -20,4 +20,7 @@ architecture arch of gate is
begin
assert false report msg;
inst1: entity work.ent1 port map (s);
inst2: comp port map (s);
inst3: component comp port map (s);
inst4: entity work.ent1(arch) port map (s);
end arch;
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