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Commit 8a945172 authored by Tristan Gingold's avatar Tristan Gingold
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vhdl_parser: adjust regexp

parent 0b6ba299
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hdlmake/sourcefiles/vhdl_parser.py
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......@@ -221,7 +221,7 @@ class VHDLParser(DepParser):
r"^\s*(?P<LABEL>\w+)\s*:"
r"\s*(?:entity\s+(?P<LIB>\w+)\.)?(?P<ENTITY>\w+)"
r"\s*(?:\(\s*(?P<ARCH>\w+)\s*\)\s*)?"
r"(?:port|generic)\s+map.*?",
r"(?:port|generic)\s+map.*?;",
re.DOTALL | re.MULTILINE | re.IGNORECASE)
def do_instance(text):
......
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