Implement Microsemi IP Core parsing; finds cxf deps w/o a manifest

80e7a57b · Christos Gentsos · b961c9b8 · 80e7a57b · 80e7a57b · 80e7a57b
Commit 80e7a57b authored Apr 09, 2020 by Christos Gentsos
Showing with 98 additions and 4 deletions

cxf_parser.py hdlmake/sourcefiles/cxf_parser.py +75 -0

sourcefileset.py hdlmake/sourcefiles/sourcefileset.py +9 -1

srcfile.py hdlmake/sourcefiles/srcfile.py +11 -1

liberosoc.py hdlmake/tools/liberosoc.py +3 -2

No files found.
--- a/hdlmake/sourcefiles/cxf_parser.py
+++ b/hdlmake/sourcefiles/cxf_parser.py
+#!/usr/bin/python
+#
+# Author: Christos Gentsos
+#
+# This file is part of Hdlmake.
+#
+# Hdlmake is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# Hdlmake is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with Hdlmake.  If not, see .
+#
+
+"""This module provides a Microsemi CXF IP description parser for HDLMake"""
+
+from __future__ import absolute_import
+import re
+import logging
+
+from xml.etree import ElementTree as ET
+
+from .new_dep_solver import DepParser
+from .dep_file import DepRelation
+from ..sourcefiles.srcfile import create_source_file
+
+class CXFParser(DepParser):
+    """Class providing the Microsemi CXF parser"""
+
+    def __init__(self, dep_file):
+        self.hdldeps = []
+        DepParser.__init__(self, dep_file)
+
+    def parse(self, dep_file):
+        """Parse a Microsemi CXF IP description file to determine the provided module(s)"""
+        assert not dep_file.is_parsed
+        logging.debug("Parsing %s in library %s", dep_file.path, dep_file.library)
+
+        with open(dep_file.path) as f:
+            xml = f.read()
+            # extract namespaces with a regex
+            xmlnsre = re.compile(r'\bxmlns\s*=\s*"(\w+://[^"]*)"', re.MULTILINE)
+            nsobj = xmlnsre.search(xml)
+            try:
+                ns = '{'+nsobj.group(1)+'}'
+            except e:
+                ns = ''
+
+            # find the IP core name
+            xmlET = ET.fromstring(xml)
+            nameobj = xmlET.find(ns+'name')
+            try:
+                module_name = nameobj.text
+            except e:
+                module_name = None
+
+            # gather the list of source files
+            for i in xmlET.iter(ns+'file'):
+                for ii in i.iter(ns+'name'):
+                    if ii.text.endswith(('.vhd', '.cxf')):
+                        dep_file.included_files.add(ii.text)
+
+            if not module_name is None:
+                logging.debug("found module %s.%s", dep_file.library, module_name)
+                # dep_file.add_provide(
+                #     DepRelation(module_name, dep_file.library, DepRelation.MODULE))
+
+        logging.debug("%s has %d includes.", str(dep_file), len(dep_file.included_files))
+        dep_file.is_parsed = True
--- a/hdlmake/sourcefiles/sourcefileset.py
+++ b/hdlmake/sourcefiles/sourcefileset.py
@@ -19,6 +19,8 @@
 #

 from .dep_file import File
+from .srcfile import CXFFile, create_source_file
+import os
 import logging

 class SourceFileSet(set):
@@ -36,7 +38,13 @@ class SourceFileSet(set):
        if files is None:
            logging.debug("Got None as a file.\n Ommiting")
            return
-        if isinstance(files, (SourceFileSet, set)):
+        if isinstance(files, CXFFile):
+            if not files.is_parsed:
+                files.parser.parse(files)
+                for f in files.included_files:
+                    path_abs = os.path.abspath(os.path.dirname(files.path) + '/' + f)
+                    super(SourceFileSet, self).add(create_source_file(path_abs, files.module))
+        elif isinstance(files, (SourceFileSet, set)):
            for file_aux in files:
                super(SourceFileSet, self).add(file_aux)
        else:

--- a/hdlmake/sourcefiles/srcfile.py
+++ b/hdlmake/sourcefiles/srcfile.py
@@ -244,9 +244,17 @@ class PDCFile(File):
    """Physical Design Constraints"""
    pass

+class CXFFile(SourceFile):
+    """Microsemi IP core File"""
+
+    def __init__(self, path, module, library=None):
+        SourceFile.__init__(self, path=path, module=module, library=library)
+        from .cxf_parser import CXFParser
+        self.parser = CXFParser(self)

 MICROSEMI_FILE_DICT = {
-    'pdc': PDCFile}
+    'pdc': PDCFile,
+    'cxf': CXFFile}


 # OHR FILES
@@ -348,6 +356,8 @@ def create_source_file(path, module, library=None, include_dirs=None):
        new_file = SDCFile(path=path, module=module)
    elif extension == 'xci':
        new_file = XCIFile(path=path, module=module, library=library)
+    elif extension == 'cxf':
+        new_file = CXFFile(path=path, module=module, library=library)
    elif extension in XILINX_FILE_DICT:
        new_file = XILINX_FILE_DICT[extension](path=path, module=module)
    elif extension in ALTERA_FILE_DICT:

--- a/hdlmake/tools/liberosoc.py
+++ b/hdlmake/tools/liberosoc.py
@@ -27,7 +27,7 @@

 from __future__ import absolute_import
 from .makefilesyn import MakefileSyn
-from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile
+from ..sourcefiles.srcfile import VHDLFile, VerilogFile, SDCFile, PDCFile, CXFFile


 class ToolLiberoSoC(MakefileSyn):
@@ -51,7 +51,8 @@ class ToolLiberoSoC(MakefileSyn):

    HDL_FILES = {
        VHDLFile: _LIBERO_SOURCE.format('-hdl_source'),
-        VerilogFile: _LIBERO_SOURCE.format('-hdl_source')}
+        VerilogFile: _LIBERO_SOURCE.format('-hdl_source'),
+        CXFFile: ''}

    CLEAN_TARGETS = {'clean': ["$(PROJECT)"],
                     'mrproper': ["*.pdb", "*.stp"]}