Issues · Projects / Hdlmake · Open Hardware Repository

Allow absolute paths in manifests

#94 · opened May 01, 2019 by Nicolas Chevillot
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updated May 01, 2019
Expand environment variables in module/files paths

#93 · opened May 01, 2019 by Nicolas Chevillot
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updated May 01, 2019
quit functions should not be called except in main function

#92 · opened Apr 30, 2019 by Nicolas Chevillot
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- 1
updated Apr 30, 2019
In case an option in a Manifest uses a type which is not allowed, the error message is highly cryptic and doesn't help to solve the issue

#91 · opened Apr 30, 2019 by Nicolas Chevillot
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updated Apr 30, 2019
--sufix command is a typo => rename to --suffix for proper english

#90 · opened Apr 30, 2019 by Nicolas Chevillot bug
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updated Apr 30, 2019
Add an option to display full error log in case of an error

#89 · opened Apr 29, 2019 by Nicolas Chevillot feature
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updated Apr 30, 2019
VHDL parser should create relations for package without library

#12 · opened Nov 15, 2016 by Nicolas Chevillot bug
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updated Mar 30, 2019
multitline signal declaration generates wrong relations in VHDL

#13 · opened Nov 14, 2016 by Nicolas Chevillot bug
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updated Feb 12, 2019
String Element inside $display Verilog function will be misinterpreted as module

#17 · opened Jun 02, 2016 by Andreas Bergmann bug
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updated Mar 30, 2019
Relations missing for VHDL package to be used in system verilog

#20 · opened Jun 01, 2016 by Nicolas Chevillot bug
- 6
updated Feb 12, 2019
Parameter is misinterprated and misinterpreted as (missing) module

#34 · opened Apr 13, 2016 by Andreas Bergmann (Consult) bug
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updated Mar 30, 2019
support of VHDL, SystemVerilog configuration blocks

#49 · opened Nov 18, 2014 by Adrian Fiergolski feature
- 0
updated Feb 12, 2019