Issues · Projects / Hdlmake · Open Hardware Repository

Cannot simulate or synthesize if I have multiple vhdl files

#98 · opened Aug 15, 2019 by Karthik Selvan
- 0
updated Aug 15, 2019
Add test to check validity of parameters in manifests

#97 · opened Jun 03, 2019 by Nicolas Chevillot
- 3
updated Jun 04, 2019
DISCUSSION: Find the best way to support 'attirbutes' kind for modules or files

#96 · opened Jun 03, 2019 by Nicolas Chevillot feature
- 9
updated Jun 04, 2019
DISCUSSION: getting rid of parsers (and automatic dependencies)

#95 · opened Jun 03, 2019 by Tristan Gingold
- 2
updated Jun 04, 2019
Allow absolute paths in manifests

#94 · opened May 01, 2019 by Nicolas Chevillot
- 1
- 0
updated May 01, 2019
Expand environment variables in module/files paths

#93 · opened May 01, 2019 by Nicolas Chevillot
- 0
updated Jun 03, 2019
VHDL parser should create relations for package without library

#12 · opened Nov 15, 2016 by Nicolas Chevillot bug
- 1
updated Mar 30, 2019
multitline signal declaration generates wrong relations in VHDL

#13 · opened Nov 14, 2016 by Nicolas Chevillot bug
- 0
updated Feb 12, 2019
String Element inside $display Verilog function will be misinterpreted as module

#17 · opened Jun 02, 2016 by Andreas Bergmann bug
- 2
updated Mar 30, 2019
Relations missing for VHDL package to be used in system verilog

#20 · opened Jun 01, 2016 by Nicolas Chevillot bug
- 6
updated Feb 12, 2019
Parameter is misinterprated and misinterpreted as (missing) module

#34 · opened Apr 13, 2016 by Andreas Bergmann (Consult) bug
- 1
updated Mar 30, 2019
support of VHDL, SystemVerilog configuration blocks

#49 · opened Nov 18, 2014 by Adrian Fiergolski feature
- 0
updated Feb 12, 2019