Hdlmake
Hdlmake is a tool for generating multi-purpose makefiles for FPGA projects. It's main features are:
- makefile generation for:
- fetching modules from repositories
- simulating HDL projects
- synthesizing HDL projects
- synthesizing projects remotely (keeping your local resources free)
- generating multi-vendor project files (no clicking in the IDE!)
- many other things without involving make and makefiles
Hdlmake generates multi-purpose makefiles for HDL projects management. It supports synthesis, simulation, fetching module dependencies from repositories, creating project for multiple FPGA toolchains... All of this can be done with a makefile command or with Hdlmake directly. It supports modularity, scalability, use of revision control systems and code reuse. Hdlmake is free, open and distributed under the GPL license.
Features
Supported Tools
| Tool | Synthesis | Simulation |
|---|---|---|
| Xilinx ISE | Yes | n.a. |
| Xilinx PlanAhead | Yes | n.a. |
| Xilinx Vivado | Yes | Yes |
| Altera Quartus | Yes | n.a. |
| Microsemi (Actel) Libero | Yes | n.a. |
| Lattice Semi. Diamond | Yes | n.a. |
| Project IceStorm | Verilog | n.a. |
| Xilinx ISim | n.a. | Yes |
| Mentor Graphics Modelsim | n.a. | Yes |
| Mentor Graphics Questa | n.a. | Yes |
| Aldec Active-HDL | n.a. | Yes |
| Aldec Riviera-PRO | n.a. | Yes |
| Icarus Verilog | n.a. | Yes |
| GHDL | n.a. | VHDL |
Supported Operating Systems
| Operating System | Comments |
|---|---|
| Linux | tested on Ubuntu Precise/Trusty/Xenial, CentOS 6/7 |
| Windows | tested on Windows 7/8/8.1/10 for CMD and PowerShell |
Supported Python Version
| Version | Comments |
|---|---|
| Python 2 | Runs on 2.7 |
| Python 3 | Runs on 3.x |
Documentation
Hdlmake docs are written by using Sphinx and hosted in Read the docs in order to allow an agile managament for the documentation related with the different code branches and releases.
- Browse hdlmake docs
- Download hdlmake docs:
These are some valuable resources included in the wiki pages:
- FAQ
- Program map with diagrams and tips
- Developer Guidelines
- Ideas for enhancements
- HDLMake vs FuseSoC
These pages include instructions on how to build and simulate the reference designs for White Rabbit PTP Core v4.2 by using HDLMake v3:
Previous Releases
ISYP
ISYP is the name of the original hdlmake release written by Pawel Szostek. Most of the HDL projects hosted in the Open Hardware Repository rely on this stable version, so you can find more info about it via the following links:
In order to migrate an old HDLMake project to the new version, you should check the following guidelines:
Contacts
Commercial Support
- GL Research provides commercial consulting and training services for advanced hdlmake use cases.
General Questions
Status
| Date | Event |
|---|---|
| 16-08-2010 | Project creation |
| 05-05-2013 | Version 1.0 published (A.K.A. ISYP), featuring support for Xilinx ISE synthesis and Mentor Modelsim simulation |
| 03-04-2014 | Custom version 1.1, crafted under GSI requirements and supporting Altera Quartus designs |
| 09-10-2014 | Version 2.0 published and introduced at the 8th White Rabbit workshop. Aimed to provide multi-tool support |
| 28-03-2015 | Version 2.1 published, featuring incremental improvements over the previous release |
| 19-09-2016 | Developer beta for version 3.0 released for user input driven debugging |
| 26-05-2017 | Version 3.0 published, featuring native Windows shell and Python 2.7 / 3.x support |
| 16-02-2018 | Add some enhancements ideas |
| 30-03-2019 | Version 3.1 published, including bug-fixes and improvements |
| 11-04-2019 | Version 3.2 published, fixed Quartus and Verilog/SystemVerilog support in synthesis |
Javier Garcia-Lasheras - April 2019