Commit c0522d30 authored by Tristan Gingold's avatar Tristan Gingold

Add test for previous commit.

parent d6694bf2
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
TOP_MODULE := gate
MODELSIM_INI_PATH := ../linux_fakebin/..
VCOM_FLAGS := -quiet -modelsimini modelsim.ini
VSIM_FLAGS :=
VLOG_FLAGS := -quiet -modelsimini modelsim.ini
VMAP_FLAGS := -modelsimini modelsim.ini
#target for performing local simulation
local: sim_pre_cmd simulation sim_post_cmd
VERILOG_SRC :=
VERILOG_OBJ :=
VHDL_SRC := gate.vhdl \
VHDL_OBJ := work/hdlmake/gate_vhdl \
INCLUDE_DIRS :=
LIBS := work
LIB_IND := work/hdlmake/work-stamp
simulation: modelsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): modelsim.ini
$(VHDL_OBJ): $(LIB_IND) modelsim.ini
modelsim.ini: $(MODELSIM_INI_PATH)/modelsim.ini
cp $< . 2>&1
work/hdlmake/work-stamp:
(vlib work && vmap $(VMAP_FLAGS) work && mkdir -p work/hdlmake && touch work/hdlmake/work-stamp) || rm -rf work
work/hdlmake/gate_vhdl: gate.vhdl
vcom $(VCOM_FLAGS) -work work $<
@touch $@
# USER SIM COMMANDS
sim_pre_cmd:
sim_post_cmd:
CLEAN_TARGETS := $(LIBS) modelsim.ini transcript
clean:
rm -rf $(CLEAN_TARGETS)
mrproper: clean
rm -rf *.vcd *.wlf
.PHONY: mrproper clean sim_pre_cmd sim_post_cmd simulation
action = "simulation"
sim_tool="modelsim"
top_module = "gate"
files = [ "gate.vhdl" ]
use work.all;
entity gate is
end;
architecture arch of gate is
begin
assert false report msg;
end arch;
......@@ -282,9 +282,12 @@ def test_gitsm_fetch026():
hdlmake.main.hdlmake(['fetch'])
shutil.rmtree('ipcores')
def test_vhdl_parser():
def test_vhdl_parser027():
run_compare(path="027vhdl_parser")
def test_vhdl_parser100():
run_compare(path="100vhdl_parser")
def test_manifest_print():
run([], path="028manifest_print")
os.remove('028manifest_print/Makefile')
......
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