Commit 2366d4f2 authored by Tristan Gingold's avatar Tristan Gingold

Clean libraries for ghdl.

parent c227a82a
......@@ -62,6 +62,8 @@ class ToolGHDL(MakefileSim):
def _makefile_sim_compilation(self):
"""Print the GDHL simulation compilation target"""
libs = self.get_all_libs()
self._makefile_sim_libs_variables(libs)
self.writeln("simulation: $(VERILOG_OBJ) $(VHDL_OBJ)")
self.writeln("\t\t" + self.SIMULATOR_CONTROLS['compiler'])
self.writeln('\n')
......
......@@ -19,6 +19,9 @@ VHDL_SRC := ../files/gate.vhdl \
VHDL_OBJ := work/gate/.gate_vhdl \
work/gate3/.gate3_vhd \
LIBS := work
LIB_IND := work/.work
simulation: $(VERILOG_OBJ) $(VHDL_OBJ)
$(GHDL) -e $(GHDL_OPT) $(TOP_MODULE)
......
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