Bug fix in L2P DMA FSM, was checking l_wr_rdy only before sendind the 1st packet and not for the next packets in case of data split into several packets. Long DMA were causing the GN4124 chip to crash.

Remove stall signal from stb generation, -> all read data from fifo are strobed to the wishbone bus.

Uses serdes and PLL for clocking.
IODELAY are bypassed on data inputs lines.
System clock in shifted 90deg compared to input p2l clock.