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Commit 8d4c53cc authored by Matthieu Cattin's avatar Matthieu Cattin
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Add generic to define if the target is spartan 6 and implement the primitives accordingly

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hdl/gn4124core/design/rtl/gn4124_core.vhd
+ 25
− 11
View file @ 8d4c53cc
......@@ -40,11 +40,12 @@ use UNISIM.vcomponents.all;
--==============================================================================
entity gn4124_core is
generic(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
g_IS_SPARTAN6 : boolean := false; -- This generic is used to instanciate spartan6 specific primitives
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
-- => number of bits to address periph on the board
g_CSR_WB_SLAVES_NB : integer := 1; -- Number of CSR wishbone slaves
g_DMA_WB_SLAVES_NB : integer := 1; -- Number of DMA wishbone slaves
g_DMA_WB_ADDR_WIDTH : integer := 26 -- DMA wishbone address bus width
);
port
(
......@@ -320,11 +321,18 @@ begin
end if;
end process p_core_rst;
cmp_rst_buf : BUFG
port map (
I => rst_reg,
O => rst_n
);
gen_rst : if g_IS_SPARTAN6 = false generate
cmp_rst_buf : BUFG
port map (
I => rst_reg,
O => rst_n
);
end generate gen_rst;
gen_rst_s6 : if g_IS_SPARTAN6 = true generate
rst_n <= rst_reg;
end generate gen_rst_s6;
------------------------------------------------------------------------------
-- IRQ pulse forward to GN4124 GPIO
......@@ -339,6 +347,9 @@ begin
-- p2l_des: Deserialize the P2L DDR inputs
-----------------------------------------------------------------------------
cmp_p2l_des : p2l_des
generic map (
g_IS_SPARTAN6 => g_IS_SPARTAN6
)
port map
(
---------------------------------------------------------
......@@ -425,7 +436,7 @@ begin
generic map
(
g_BAR0_APERTURE => g_BAR0_APERTURE,
g_WB_SLAVES_NB => (g_CSR_WB_SLAVES_NB + 1) -- +1 for the DMA controller (wb slave always present)
g_WB_SLAVES_NB => (g_CSR_WB_SLAVES_NB + 1) -- +1 for the DMA controller (wb slave always present)
)
port map
(
......@@ -754,6 +765,9 @@ begin
-- L2P_SER: Generate the L2P DDR Outputs
-----------------------------------------------------------------------------
cmp_l2p_ser : l2p_ser
generic map (
g_IS_SPARTAN6 => g_IS_SPARTAN6
)
port map
(
---------------------------------------------------------
......
hdl/gn4124core/design/rtl/gn4124_core_pkg.vhd
+ 14
− 18
View file @ 8d4c53cc
......@@ -53,7 +53,9 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component p2l_des
-----------------------------------------------------------------------------
generic (
g_IS_SPARTAN6 : boolean := false
);
port
(
---------------------------------------------------------
......@@ -82,7 +84,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component p2l_decode32
-----------------------------------------------------------------------------
port
(
---------------------------------------------------------
......@@ -125,7 +126,9 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component l2p_ser
-----------------------------------------------------------------------------
generic (
g_IS_SPARTAN6 : boolean := false
);
port
(
---------------------------------------------------------
......@@ -151,7 +154,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component wbmaster32
-----------------------------------------------------------------------------
generic
(
g_BAR0_APERTURE : integer := 20; -- BAR0 aperture, defined in GN4124 PCI_BAR_CONFIG register (0x80C)
......@@ -201,21 +203,20 @@ package gn4124_core_pkg is
---------------------------------------------------------
-- CSR wishbone interface
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_clk_i : in std_logic; -- Wishbone bus clock
wb_adr_o : out std_logic_vector(g_BAR0_APERTURE-log2_ceil(g_WB_SLAVES_NB)-1 downto 0); -- Address
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
wb_dat_o : out std_logic_vector(31 downto 0); -- Data out
wb_sel_o : out std_logic_vector(3 downto 0); -- Byte select
wb_stb_o : out std_logic; -- Strobe
wb_we_o : out std_logic; -- Write
wb_cyc_o : out std_logic_vector(g_WB_SLAVES_NB-1 downto 0); -- Cycle
wb_dat_i : in std_logic_vector((32*g_WB_SLAVES_NB)-1 downto 0); -- Data in
wb_ack_i : in std_logic_vector(g_WB_SLAVES_NB-1 downto 0) -- Acknowledge
);
end component; -- wbmaster32
-----------------------------------------------------------------------------
component dma_controller
-----------------------------------------------------------------------------
port
(
---------------------------------------------------------
......@@ -268,7 +269,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component l2p_dma_master
-----------------------------------------------------------------------------
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
......@@ -323,7 +323,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component p2l_dma_master
-----------------------------------------------------------------------------
generic (
-- Enable byte swap module (if false, no swap)
g_BYTE_SWAP : boolean := false
......@@ -405,7 +404,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component l2p_arbiter
-----------------------------------------------------------------------------
port (
---------------------------------------------------------
-- Clock/Reset
......@@ -446,7 +444,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component fifo_32x512
-----------------------------------------------------------------------------
port (
rst : in std_logic;
wr_clk : in std_logic;
......@@ -465,7 +462,6 @@ package gn4124_core_pkg is
-----------------------------------------------------------------------------
component fifo_64x512
-----------------------------------------------------------------------------
port (
rst : in std_logic;
wr_clk : in std_logic;
......
hdl/gn4124core/design/rtl/l2p_ser.vhd
+ 70
− 24
View file @ 8d4c53cc
......@@ -33,6 +33,9 @@ use UNISIM.vcomponents.all;
entity l2p_ser is
generic (
g_IS_SPARTAN6 : boolean := false
);
port
(
---------------------------------------------------------
......@@ -122,20 +125,44 @@ begin
------------------------------------------------------------------------------
-- DDR FF instanciation for data
------------------------------------------------------------------------------
DDROUT : for i in 0 to 15 generate
U : OFDDRRSE
port map
(
Q => l2p_data_o(i),
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D0 => data_d(i),
D1 => data_d(i+16),
R => ff_rst,
S => '0'
);
end generate;
-- Spartan3 primitives instanciation
gen_out_ddr_ff : if g_IS_SPARTAN6 = false generate
-- Data
DDROUT : for i in 0 to 15 generate
U : OFDDRRSE
port map
(
Q => l2p_data_o(i),
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D0 => data_d(i),
D1 => data_d(i+16),
R => ff_rst,
S => '0'
);
end generate;
end generate gen_out_ddr_ff;
-- Spartan6 primitives instanciation
gen_out_ddr_ff_s6 : if g_IS_SPARTAN6 = true generate
-- Data
DDROUT : for i in 0 to 15 generate
U : ODDR2
port map
(
Q => l2p_data_o(i),
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D0 => data_d(i),
D1 => data_d(i+16),
R => ff_rst,
S => '0'
);
end generate;
end generate gen_out_ddr_ff_s6;
------------------------------------------------------------------------------
-- DDR source synchronous clock generation
......@@ -146,16 +173,35 @@ begin
OB => l2p_clk_n_o,
I => l2p_clk_sdr);
L2P_CLK_int : FDDRRSE
port map(
Q => l2p_clk_sdr,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
-- Spartan3 primitives instanciation
gen_l2p_clk_ddr_ff : if g_IS_SPARTAN6 = false generate
-- L2P clock
L2P_CLK_int : FDDRRSE
port map(
Q => l2p_clk_sdr,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate gen_l2p_clk_ddr_ff;
-- Spartan6 primitives instanciation
gen_l2p_clk_ddr_ff_s6 : if g_IS_SPARTAN6 = true generate
-- L2P clock
L2P_CLK_int : ODDR2
port map(
Q => l2p_clk_sdr,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D0 => '1',
D1 => '0',
R => '0',
S => '0');
end generate gen_l2p_clk_ddr_ff_s6;
end rtl;
......
hdl/gn4124core/design/rtl/p2l_des.vhd
+ 126
− 31
View file @ 8d4c53cc
......@@ -32,6 +32,9 @@ use UNISIM.vcomponents.all;
entity p2l_des is
generic (
g_IS_SPARTAN6 : boolean := false
);
port
(
---------------------------------------------------------
......@@ -67,7 +70,8 @@ architecture rtl of p2l_des is
-----------------------------------------------------------------------------
-- DDR FF reset
signal ff_rst : std_logic;
signal ff_rst : std_logic;
signal p2l_data_d : std_logic_vector(p2l_data_i'range);
-- SDR signals
signal p2l_valid_p : std_logic;
......@@ -98,46 +102,137 @@ begin
------------------------------------------------------------------------------
-- DDR FF instanciation
------------------------------------------------------------------------------
DDRFF_D : for i in p2l_data_i'range generate
U : IFDDRRSE
-- Spartan3 primitives instanciation
gen_in_ddr_ff : if g_IS_SPARTAN6 = false generate
-- Data
DDRFF_D : for i in p2l_data_i'range generate
U : IFDDRRSE
port map
(
Q0 => p2l_data_n(i),
Q1 => p2l_data_p(i),
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_data_i(i),
R => ff_rst,
S => '0'
);
end generate;
-- dframe
DDRFF_F : IFDDRRSE
port map
(
Q0 => p2l_data_n(i),
Q1 => p2l_data_p(i),
Q0 => p2l_dframe_n,
Q1 => p2l_dframe_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_data_i(i),
D => p2l_dframe_i,
R => ff_rst,
S => '0'
);
end generate;
DDRFF_F : IFDDRRSE
port map
(
Q0 => p2l_dframe_n,
Q1 => p2l_dframe_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_dframe_i,
R => ff_rst,
S => '0'
);
-- valid
DDRFF_V : IFDDRRSE
port map
(
Q0 => p2l_valid_n,
Q1 => p2l_valid_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_valid_i,
R => ff_rst,
S => '0'
);
end generate gen_in_ddr_ff;
DDRFF_V : IFDDRRSE
port map
(
Q0 => p2l_valid_n,
Q1 => p2l_valid_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_valid_i,
R => ff_rst,
S => '0'
);
-- Spartan6 primitives instanciation
gen_in_ddr_ff_s6 : if g_IS_SPARTAN6 = true generate
gen_in_delay : for i in p2l_data_i'range generate
-- Input delay
cmp_din_delay : IODELAY2
generic map (
COUNTER_WRAPAROUND => "WRAPAROUND", -- STAY_AT_LIMIT or WRAPAROUND
DATA_RATE => "DDR", -- SDR or DDR
DELAY_SRC => "IDATAIN", -- IO, ODATAIN or IDATAIN
IDELAY2_VALUE => 0, -- Amount of Input Delay (0-255)
IDELAY_MODE => "NORMAL", -- Unsupported
IDELAY_TYPE => "FIXED", -- FIXED, DEFAULT, VARIABLE_FROM_ZERO, VARIABLE_FROM_HALF_MAX or
-- DIFF_PHASE_DETECTOR
IDELAY_VALUE => 120, -- Amount of input delay (0-255)
ODELAY_VALUE => 0, -- Amount of output delay (0-255)
SERDES_MODE => "NONE", -- NONE, MASTER or SLAVE
SIM_TAPDELAY_VALUE => 75 -- Amount of delay used for simulation in pS
)
port map (
BUSY => open, -- 1-bit Busy after CAL
DATAOUT => p2l_data_d(i), -- 1-bit Delayed data output to ISERDES/Input register
DATAOUT2 => open, -- 1-bit Delayed data output to general FPGA fabric
DOUT => open, -- 1-bit Delayed Data Output to IOB
TOUT => open, -- 1-bit Delayed Tristate Output
CAL => '0', -- 1-bit Initiate calibration input
CE => '0', -- 1-bit Enable increment/decrement
CLK => '0', -- 1-bit Clock input
IDATAIN => p2l_data_i(i), -- 1-bit Data Signal from IOB
INC => '0', -- 1-bit Increment / Decrement input
-- IOCLK0 - IOCLK1: 1-bit (each) I/O Clock inputs
IOCLK0 => '0',
IOCLK1 => '0',
ODATAIN => '0', -- 1-bit Output data input from OLOGIC or OSERDES.
RST => '0', -- 1-bit Reset to zero or 1/2 of total period
T => '0' -- 1-bit Tristate input signal
);
end generate;
-- Data
DDRFF_D : for i in p2l_data_i'range generate
U : IDDR2
port map
(
Q0 => p2l_data_n(i),
Q1 => p2l_data_p(i),
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_data_d(i),
R => ff_rst,
S => '0'
);
end generate;
-- dframe
DDRFF_F : IDDR2
port map
(
Q0 => p2l_dframe_n,
Q1 => p2l_dframe_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_dframe_i,
R => ff_rst,
S => '0'
);
-- valid
DDRFF_V : IDDR2
port map
(
Q0 => p2l_valid_n,
Q1 => p2l_valid_p,
C0 => clk_n_i,
C1 => clk_p_i,
CE => '1',
D => p2l_valid_i,
R => ff_rst,
S => '0'
);
end generate gen_in_ddr_ff_s6;
-----------------------------------------------------------------------------
......
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