- 16 Jan, 2023 7 commits
-
-
Tristan Gingold authored
Adding Testbench for AXI cores See merge request !28
-
kblantos authored
-
kblantos authored
Correct License added. Fixes done in order to solve the issue with axi4lite_axi4full_bridge assertion. sim_top_ps_gpio now not run forever
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
Dimitris Lampridis authored
-
- 13 Jan, 2023 2 commits
- 16 Dec, 2022 2 commits
-
-
Tomasz Wlostowski authored
2 new WB cores See merge request !26
-
Dimitris Lampridis authored
Genrams improvements See merge request !25
-
- 15 Dec, 2022 9 commits
-
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
Wraps an LM32, DPRAM, UART and indirect memory loader.
-
Tomasz Wlostowski authored
-
Tomasz Wlostowski authored
genrams: added g_implementation_hint RAM/FIFO attribute allowing to select the memory primitive used to implement the RAM. Currently only works on Xilinx FPGAs (the choices being "ultra", "block", "distributed", and the default "auto") and is ignored in other platforms.
-
Tomasz Wlostowski authored
inferred_async_fifo: avoid nested 'others' clause in signal initialization to keep ISE (Virtex5) happy
-
- 10 Oct, 2022 1 commit
-
-
Pascal Bos authored
Issue occurred when "wb.ack" became active in the same cycle as "wb.stall" became inactive. The "RESPONSE_READ" state was skipped and therefore a proper handshake with the axilite bus wasn't guaranteed.
-
- 01 Sep, 2022 1 commit
-
-
Tristan Gingold authored
-
- 18 Jul, 2022 1 commit
-
-
Tristan Gingold authored
hdl/sim: Protect CIWBMasterAccessor against multiple requests See merge request !19
-
- 16 Jul, 2022 1 commit
-
-
Dimitris Lampridis authored
When performing reads/writes from multiple threads, CIWBMasterAccessor does not provide any protection, leading to data from one request being delivered to another. By replacing the data queues with SV mailboxes, we ensure that only one thread can access the mailbox at any given time. Furthermore, we add a SV event in wb_cycle_t, which is used to notify the readm()/writem() tasks that their transfer is complete, to avoid getting the result of the wrong transfer.
-
- 28 Jun, 2022 16 commits
-
-
David Belohrad authored
components purely dependent of xilinx libraries are not compiled in if target differs from xilinx
-
David Belohrad authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-
Tristan Gingold authored
-