radtol: improve secdec_32b package and tb

21cd321f · Tristan Gingold · c7593f46 · 21cd321f · 21cd321f
Commit 21cd321f authored Jun 28, 2022 by Tristan Gingold
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Showing with 17 additions and 2 deletions

secded_32b_pkg.vhd modules/radtol/secded_32b_pkg.vhd +2 -2

tb_secded_32b_pkg.vhd testbench/radtol/tb_secded_32b_pkg.vhd +15 -0

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--- a/modules/radtol/secded_32b_pkg.vhd
+++ b/modules/radtol/secded_32b_pkg.vhd
@@ -4,9 +4,9 @@
 -- https://www.ohwr.org/projects/general-cores
 --------------------------------------------------------------------------------
 --
-- unit name:   secded_ecc
+-- unit name:   secded_32b_pkg
 --
-- description: SECDED RAM controller
+-- description: ECC on 32b
 --
 --------------------------------------------------------------------------------
 -- Copyright CERN 2020-2021

--- a/testbench/radtol/tb_secded_32b_pkg.vhd
+++ b/testbench/radtol/tb_secded_32b_pkg.vhd
@@ -24,9 +24,24 @@ architecture behav of tb_secded_32b_pkg is
  signal orig_data, data : std_logic_vector (31 downto 0);
  signal orig_ecc, ecc, comp_ecc, syndrome : std_logic_vector(6 downto 0);
  signal err, cor : std_logic_vector(38 downto 0);
+
+  type vectors_type is
+    array (natural range <>) of std_logic_vector(31 downto 0);
+  constant vectors : vectors_type :=
+    (x"00001197",
+     x"22c18193",
+     x"00040117",
+     x"ffffffff");
+  
 begin
  process
+    variable ecc2 : std_logic_vector(6 downto 0);
  begin
+    for i in vectors'range loop
+      ecc2 := f_calc_ecc (vectors (i));
+      report "data:  " & to_hstring (vectors (i)) & ", ecc:  " & to_hstring (ecc2);
+    end loop;
+
    orig_data <= x"789a_d3f5";
    syndrome <= "0000000";
    wait for 1 ns;